2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/sizes.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/iomux.h>
18 #include <asm/arch/mx6-pins.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/imx-common/iomux-v3.h>
22 DECLARE_GLOBAL_DATA_PTR
;
24 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
25 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
26 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
28 static iomux_v3_cfg_t
const uart4_pads
[] = {
29 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
30 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
33 int board_early_init_f(void)
35 SETUP_IOMUX_PADS(uart4_pads
);
42 /* Address of boot parameters */
43 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
50 gd
->ram_size
= imx_ddr_size();
55 #ifdef CONFIG_SPL_BUILD
59 #include <asm/arch/crm_regs.h>
60 #include <asm/arch/mx6-ddr.h>
62 /* MMC board initialization is needed till adding DM support in SPL */
63 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
65 #include <fsl_esdhc.h>
67 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
68 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
69 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
71 static iomux_v3_cfg_t
const usdhc3_pads
[] = {
72 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
73 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
74 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
75 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
76 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
77 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
80 struct fsl_esdhc_cfg usdhc_cfg
[1] = {
81 {USDHC3_BASE_ADDR
, 1, 4},
84 int board_mmc_getcd(struct mmc
*mmc
)
86 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
89 switch (cfg
->esdhc_base
) {
90 case USDHC3_BASE_ADDR
:
98 int board_mmc_init(bd_t
*bis
)
103 * According to the board_mmc_init() the following map is done:
104 * (U-boot device node) (Physical Port)
107 for (i
= 0; i
< CONFIG_SYS_FSL_USDHC_NUM
; i
++) {
110 SETUP_IOMUX_PADS(usdhc3_pads
);
111 usdhc_cfg
[i
].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
114 printf("Warning - USDHC%d controller not supporting\n",
119 ret
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[i
]);
121 printf("Warning: failed to initialize mmc dev %d\n", i
);
136 #define IMX6DQ_DRIVE_STRENGTH 0x30
137 #define IMX6SDL_DRIVE_STRENGTH 0x28
139 /* configure MX6Q/DUAL mmdc DDR io registers */
140 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs
= {
159 .dram_sdclk_0
= 0x30,
160 .dram_sdclk_1
= 0x30,
162 .dram_sdcke0
= 0x3000,
163 .dram_sdcke1
= 0x3000,
164 .dram_sdba2
= 0x00000000,
169 /* configure MX6Q/DUAL mmdc GRP io registers */
170 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs
= {
180 .grp_ddrmode_ctl
= 0x00020000,
181 .grp_ddrpke
= 0x00000000,
182 .grp_ddrmode
= 0x00020000,
184 .grp_ddr_type
= 0x000c0000,
187 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
188 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs
= {
189 .dram_sdclk_0
= 0x30,
190 .dram_sdclk_1
= 0x30,
196 .dram_sdba2
= 0x00000000,
217 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
218 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs
= {
219 .grp_ddr_type
= 0x000c0000,
220 .grp_ddrmode_ctl
= 0x00020000,
221 .grp_ddrpke
= 0x00000000,
224 .grp_ddrmode
= 0x00020000,
236 static struct mx6_ddr3_cfg mt41j256
= {
250 static struct mx6_mmdc_calibration mx6dq_mmdc_calib
= {
251 .p0_mpwldectrl0
= 0x000E0009,
252 .p0_mpwldectrl1
= 0x0018000E,
253 .p1_mpwldectrl0
= 0x00000007,
254 .p1_mpwldectrl1
= 0x00000000,
255 .p0_mpdgctrl0
= 0x43280334,
256 .p0_mpdgctrl1
= 0x031C0314,
257 .p1_mpdgctrl0
= 0x4318031C,
258 .p1_mpdgctrl1
= 0x030C0258,
259 .p0_mprddlctl
= 0x3E343A40,
260 .p1_mprddlctl
= 0x383C3844,
261 .p0_mpwrdlctl
= 0x40404440,
262 .p1_mpwrdlctl
= 0x4C3E4446,
266 static struct mx6_ddr_sysinfo mem_q
= {
267 .ddr_type
= DDR_TYPE_DDR3
,
270 /* config for full 4GB range so that get_mem_size() works */
283 static struct mx6_mmdc_calibration mx6dl_mmdc_calib
= {
284 .p0_mpwldectrl0
= 0x001F0024,
285 .p0_mpwldectrl1
= 0x00110018,
286 .p1_mpwldectrl0
= 0x001F0024,
287 .p1_mpwldectrl1
= 0x00110018,
288 .p0_mpdgctrl0
= 0x4230022C,
289 .p0_mpdgctrl1
= 0x02180220,
290 .p1_mpdgctrl0
= 0x42440248,
291 .p1_mpdgctrl1
= 0x02300238,
292 .p0_mprddlctl
= 0x44444A48,
293 .p1_mprddlctl
= 0x46484A42,
294 .p0_mpwrdlctl
= 0x38383234,
295 .p1_mpwrdlctl
= 0x3C34362E,
299 static struct mx6_ddr_sysinfo mem_dl
= {
302 /* config for full 4GB range so that get_mem_size() works */
315 /* DDR 32bit 512MB */
316 static struct mx6_ddr_sysinfo mem_s
= {
319 /* config for full 4GB range so that get_mem_size() works */
332 static void ccgr_init(void)
334 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
336 writel(0x00003F3F, &ccm
->CCGR0
);
337 writel(0x0030FC00, &ccm
->CCGR1
);
338 writel(0x000FC000, &ccm
->CCGR2
);
339 writel(0x3F300000, &ccm
->CCGR3
);
340 writel(0xFF00F300, &ccm
->CCGR4
);
341 writel(0x0F0000C3, &ccm
->CCGR5
);
342 writel(0x000003CC, &ccm
->CCGR6
);
345 static void gpr_init(void)
347 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
349 /* enable AXI cache for VDOA/VPU/IPU */
350 writel(0xF00000CF, &iomux
->gpr
[4]);
351 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
352 writel(0x007F007F, &iomux
->gpr
[6]);
353 writel(0x007F007F, &iomux
->gpr
[7]);
356 static void spl_dram_init(void)
359 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
360 mx6_dram_cfg(&mem_s
, &mx6dl_mmdc_calib
, &mt41j256
);
361 } else if (is_mx6dl()) {
362 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
363 mx6_dram_cfg(&mem_dl
, &mx6dl_mmdc_calib
, &mt41j256
);
364 } else if (is_mx6dq()) {
365 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs
, &mx6dq_grp_ioregs
);
366 mx6_dram_cfg(&mem_q
, &mx6dq_mmdc_calib
, &mt41j256
);
372 void board_init_f(ulong dummy
)
376 /* setup AIPS and disable watchdog */
382 board_early_init_f();
387 /* UART clocks enabled and gd valid - init serial console */
388 preloader_console_init();
390 /* DDR initialization */
394 memset(__bss_start
, 0, __bss_end
- __bss_start
);
396 /* load/boot image from boot device */
397 board_init_r(NULL
, 0);