board/engicam/icorem6_rqs/icorem6_rqs.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <mmc.h>
  11
  12 #include <asm/io.h>
  13 #include <asm/gpio.h>
  14 #include <linux/sizes.h>
  15
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/crm_regs.h>
  18 #include <asm/arch/iomux.h>
  19 #include <asm/arch/mx6-pins.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/mach-imx/iomux-v3.h>
  22
  23 #include "../common/board.h"
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 #ifdef CONFIG_ENV_IS_IN_MMC
  28 int board_mmc_get_env_dev(int devno)
  29 {
  30         return devno;
  31 }
  32 #endif
  33
  34 #ifdef CONFIG_SPL_BUILD
  35 #include <spl.h>
  36
  37 /* MMC board initialization is needed till adding DM support in SPL */
  38 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
  39 #include <mmc.h>
  40 #include <fsl_esdhc.h>
  41
  42 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  43         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_HIGH |               \
  44         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  45
  46 static iomux_v3_cfg_t const usdhc3_pads[] = {
  47         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  48         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  49         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  50         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  51         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  52         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  53 };
  54
  55 static iomux_v3_cfg_t const usdhc4_pads[] = {
  56         IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  57         IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  58         IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  59         IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  60         IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  61         IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  62         IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  63         IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  64         IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  65         IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  66 };
  67
  68 struct fsl_esdhc_cfg usdhc_cfg[2] = {
  69         {USDHC3_BASE_ADDR, 1, 4},
  70         {USDHC4_BASE_ADDR, 1, 8},
  71 };
  72
  73 int board_mmc_getcd(struct mmc *mmc)
  74 {
  75         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  76         int ret = 0;
  77
  78         switch (cfg->esdhc_base) {
  79         case USDHC3_BASE_ADDR:
  80         case USDHC4_BASE_ADDR:
  81                 ret = 1;
  82                 break;
  83         }
  84
  85         return ret;
  86 }
  87
  88 int board_mmc_init(bd_t *bis)
  89 {
  90         int i, ret;
  91
  92         /*
  93         * According to the board_mmc_init() the following map is done:
  94         * (U-boot device node)    (Physical Port)
  95         * mmc0                  USDHC3
  96         * mmc1                  USDHC4
  97         */
  98         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  99                 switch (i) {
 100                 case 0:
 101                         SETUP_IOMUX_PADS(usdhc3_pads);
 102                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 103                         break;
 104                 case 1:
 105                         SETUP_IOMUX_PADS(usdhc4_pads);
 106                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 107                         break;
 108                 default:
 109                         printf("Warning - USDHC%d controller not supporting\n",
 110                                i + 1);
 111                         return 0;
 112                 }
 113
 114                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 115                 if (ret) {
 116                         printf("Warning: failed to initialize mmc dev %d\n", i);
 117                         return ret;
 118                 }
 119         }
 120
 121         return 0;
 122 }
 123
 124 #ifdef CONFIG_ENV_IS_IN_MMC
 125 void board_boot_order(u32 *spl_boot_list)
 126 {
 127         u32 bmode = imx6_src_get_boot_mode();
 128         u8 boot_dev = BOOT_DEVICE_MMC1;
 129
 130         switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
 131         case IMX6_BMODE_SD:
 132         case IMX6_BMODE_ESD:
 133                 /* SD/eSD - BOOT_DEVICE_MMC1 */
 134                 break;
 135         case IMX6_BMODE_MMC:
 136         case IMX6_BMODE_EMMC:
 137                 /* MMC/eMMC */
 138                 boot_dev = BOOT_DEVICE_MMC2;
 139                 break;
 140         default:
 141                 /* Default - BOOT_DEVICE_MMC1 */
 142                 printf("Wrong board boot order\n");
 143                 break;
 144         }
 145
 146         spl_boot_list[0] = boot_dev;
 147 }
 148 #endif
 149 #endif
 150
 151 #ifdef CONFIG_SPL_LOAD_FIT
 152 int board_fit_config_name_match(const char *name)
 153 {
 154         if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
 155                 return 0;
 156         else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
 157                 return 0;
 158         else
 159                 return -1;
 160 }
 161 #endif
 162 #endif /* CONFIG_SPL_BUILD */