board/engicam/icorem6_rqs/icorem6_rqs.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <mmc.h>
  11
  12 #include <asm/io.h>
  13 #include <asm/gpio.h>
  14 #include <linux/sizes.h>
  15
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/crm_regs.h>
  18 #include <asm/arch/iomux.h>
  19 #include <asm/arch/mx6-pins.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/mach-imx/iomux-v3.h>
  22
  23 #include "../common/board.h"
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 #ifdef CONFIG_ENV_IS_IN_MMC
  28 int board_mmc_get_env_dev(int devno)
  29 {
  30         return devno;
  31 }
  32 #endif
  33
  34 void setenv_fdt_file(void)
  35 {
  36         if (is_mx6dq())
  37                 env_set("fdt_file", "imx6q-icore-rqs.dtb");
  38         else if(is_mx6dl() || is_mx6solo())
  39                 env_set("fdt_file", "imx6dl-icore-rqs.dtb");
  40 }
  41
  42 #ifdef CONFIG_SPL_BUILD
  43 #include <spl.h>
  44
  45 /* MMC board initialization is needed till adding DM support in SPL */
  46 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
  47 #include <mmc.h>
  48 #include <fsl_esdhc.h>
  49
  50 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  51         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_HIGH |               \
  52         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  53
  54 static iomux_v3_cfg_t const usdhc3_pads[] = {
  55         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  56         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  57         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  58         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  59         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  60         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  61 };
  62
  63 static iomux_v3_cfg_t const usdhc4_pads[] = {
  64         IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  65         IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  66         IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  67         IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  68         IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  69         IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  70         IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  71         IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  72         IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  73         IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  74 };
  75
  76 struct fsl_esdhc_cfg usdhc_cfg[2] = {
  77         {USDHC3_BASE_ADDR, 1, 4},
  78         {USDHC4_BASE_ADDR, 1, 8},
  79 };
  80
  81 int board_mmc_getcd(struct mmc *mmc)
  82 {
  83         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  84         int ret = 0;
  85
  86         switch (cfg->esdhc_base) {
  87         case USDHC3_BASE_ADDR:
  88         case USDHC4_BASE_ADDR:
  89                 ret = 1;
  90                 break;
  91         }
  92
  93         return ret;
  94 }
  95
  96 int board_mmc_init(bd_t *bis)
  97 {
  98         int i, ret;
  99
 100         /*
 101         * According to the board_mmc_init() the following map is done:
 102         * (U-boot device node)    (Physical Port)
 103         * mmc0                  USDHC3
 104         * mmc1                  USDHC4
 105         */
 106         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 107                 switch (i) {
 108                 case 0:
 109                         SETUP_IOMUX_PADS(usdhc3_pads);
 110                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 111                         break;
 112                 case 1:
 113                         SETUP_IOMUX_PADS(usdhc4_pads);
 114                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 115                         break;
 116                 default:
 117                         printf("Warning - USDHC%d controller not supporting\n",
 118                                i + 1);
 119                         return 0;
 120                 }
 121
 122                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 123                 if (ret) {
 124                         printf("Warning: failed to initialize mmc dev %d\n", i);
 125                         return ret;
 126                 }
 127         }
 128
 129         return 0;
 130 }
 131
 132 #ifdef CONFIG_ENV_IS_IN_MMC
 133 void board_boot_order(u32 *spl_boot_list)
 134 {
 135         u32 bmode = imx6_src_get_boot_mode();
 136         u8 boot_dev = BOOT_DEVICE_MMC1;
 137
 138         switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
 139         case IMX6_BMODE_SD:
 140         case IMX6_BMODE_ESD:
 141                 /* SD/eSD - BOOT_DEVICE_MMC1 */
 142                 break;
 143         case IMX6_BMODE_MMC:
 144         case IMX6_BMODE_EMMC:
 145                 /* MMC/eMMC */
 146                 boot_dev = BOOT_DEVICE_MMC2;
 147                 break;
 148         default:
 149                 /* Default - BOOT_DEVICE_MMC1 */
 150                 printf("Wrong board boot order\n");
 151                 break;
 152         }
 153
 154         spl_boot_list[0] = boot_dev;
 155 }
 156 #endif
 157 #endif
 158
 159 #ifdef CONFIG_SPL_LOAD_FIT
 160 int board_fit_config_name_match(const char *name)
 161 {
 162         if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
 163                 return 0;
 164         else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
 165                 return 0;
 166         else
 167                 return -1;
 168 }
 169 #endif
 170 #endif /* CONFIG_SPL_BUILD */