board/engicam/isiotmx6ul/isiotmx6ul.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10
  11 #include <asm/io.h>
  12 #include <asm/gpio.h>
  13 #include <linux/sizes.h>
  14
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/iomux.h>
  18 #include <asm/arch/mx6-pins.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/imx-common/iomux-v3.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE | \
  25                         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  26                         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  27
  28 static iomux_v3_cfg_t const uart1_pads[] = {
  29         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  30         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  31 };
  32
  33 int board_early_init_f(void)
  34 {
  35         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  36
  37         return 0;
  38 }
  39
  40 #ifdef CONFIG_NAND_MXS
  41
  42 #define GPMI_PAD_CTRL0          (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  43 #define GPMI_PAD_CTRL1          (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  44                                 PAD_CTL_SRE_FAST)
  45 #define GPMI_PAD_CTRL2          (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  46
  47 static iomux_v3_cfg_t const nand_pads[] = {
  48         MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  49         MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  50         MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  51         MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  52         MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  53         MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  54         MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  55         MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  56         MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  57         MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  58         MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  59         MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  60         MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  61         MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  62         MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  63 };
  64
  65 static void setup_gpmi_nand(void)
  66 {
  67         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  68
  69         /* config gpmi nand iomux */
  70         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  71
  72         clrbits_le32(&mxc_ccm->CCGR4,
  73                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  74                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  75                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  76                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  77                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  78
  79         /*
  80          * config gpmi and bch clock to 100 MHz
  81          * bch/gpmi select PLL2 PFD2 400M
  82          * 100M = 400M / 4
  83          */
  84         clrbits_le32(&mxc_ccm->cscmr1,
  85                      MXC_CCM_CSCMR1_BCH_CLK_SEL |
  86                      MXC_CCM_CSCMR1_GPMI_CLK_SEL);
  87         clrsetbits_le32(&mxc_ccm->cscdr1,
  88                         MXC_CCM_CSCDR1_BCH_PODF_MASK |
  89                         MXC_CCM_CSCDR1_GPMI_PODF_MASK,
  90                         (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
  91                         (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
  92
  93         /* enable gpmi and bch clock gating */
  94         setbits_le32(&mxc_ccm->CCGR4,
  95                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  96                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  97                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  98                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  99                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 100
 101         /* enable apbh clock gating */
 102         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 103 }
 104 #endif /* CONFIG_NAND_MXS */
 105
 106 int board_init(void)
 107 {
 108         /* Address of boot parameters */
 109         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 110
 111 #ifdef CONFIG_NAND_MXS
 112         setup_gpmi_nand();
 113 #endif
 114         return 0;
 115 }
 116
 117 int dram_init(void)
 118 {
 119         gd->ram_size = imx_ddr_size();
 120
 121         return 0;
 122 }
 123
 124 #ifdef CONFIG_SPL_BUILD
 125 #include <libfdt.h>
 126 #include <spl.h>
 127
 128 #include <asm/arch/crm_regs.h>
 129 #include <asm/arch/mx6-ddr.h>
 130
 131 /* MMC board initialization is needed till adding DM support in SPL */
 132 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
 133 #include <mmc.h>
 134 #include <fsl_esdhc.h>
 135
 136 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
 137         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
 138         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 139
 140 static iomux_v3_cfg_t const usdhc1_pads[] = {
 141         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 147
 148         /* VSELECT */
 149         MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 150         /* CD */
 151         MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 152         /* RST_B */
 153         MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 154 };
 155
 156 static iomux_v3_cfg_t const usdhc2_pads[] = {
 157         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 158         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 159         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 160         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 161         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 162         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 163         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 164         MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165         MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 166 };
 167
 168 #define USDHC1_CD_GPIO  IMX_GPIO_NR(1, 19)
 169 #define USDHC2_CD_GPIO  IMX_GPIO_NR(4, 5)
 170
 171 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 172         {USDHC1_BASE_ADDR, 0, 4},
 173         {USDHC2_BASE_ADDR, 0, 8},
 174 };
 175
 176 int board_mmc_getcd(struct mmc *mmc)
 177 {
 178         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 179         int ret = 0;
 180
 181         switch (cfg->esdhc_base) {
 182         case USDHC1_BASE_ADDR:
 183                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 184                 break;
 185         case USDHC2_BASE_ADDR:
 186                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 187                 break;
 188         }
 189
 190         return ret;
 191 }
 192
 193 int board_mmc_init(bd_t *bis)
 194 {
 195         int i, ret;
 196
 197         /*
 198         * According to the board_mmc_init() the following map is done:
 199         * (U-boot device node)    (Physical Port)
 200         * mmc0                          USDHC1
 201         * mmc1                          USDHC2
 202         */
 203         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 204                 switch (i) {
 205                 case 0:
 206                         imx_iomux_v3_setup_multiple_pads(
 207                                 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 208                         gpio_direction_input(USDHC1_CD_GPIO);
 209                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 210                         break;
 211                 case 1:
 212                         imx_iomux_v3_setup_multiple_pads(
 213                                 usdhc1_pads, ARRAY_SIZE(usdhc2_pads));
 214                         gpio_direction_input(USDHC2_CD_GPIO);
 215                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 216                         break;
 217                 default:
 218                         printf("Warning - USDHC%d controller not supporting\n",
 219                                i + 1);
 220                         return 0;
 221                 }
 222
 223                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 224                 if (ret) {
 225                         printf("Warning: failed to initialize mmc dev %d\n", i);
 226                         return ret;
 227                 }
 228         }
 229
 230         return 0;
 231 }
 232
 233 #ifdef CONFIG_ENV_IS_IN_MMC
 234 void board_boot_order(u32 *spl_boot_list)
 235 {
 236         u32 bmode = imx6_src_get_boot_mode();
 237         u8 boot_dev = BOOT_DEVICE_MMC1;
 238
 239         switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
 240         case IMX6_BMODE_SD:
 241         case IMX6_BMODE_ESD:
 242                 /* SD/eSD - BOOT_DEVICE_MMC1 */
 243                 break;
 244         case IMX6_BMODE_MMC:
 245         case IMX6_BMODE_EMMC:
 246                 /* MMC/eMMC */
 247                 boot_dev = BOOT_DEVICE_MMC2;
 248                 break;
 249         default:
 250                 /* Default - BOOT_DEVICE_MMC1 */
 251                 printf("Wrong board boot order\n");
 252                 break;
 253         }
 254
 255         spl_boot_list[0] = boot_dev;
 256 }
 257 #endif
 258 #endif /* CONFIG_FSL_ESDHC */
 259
 260 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
 261         .grp_addds = 0x00000030,
 262         .grp_ddrmode_ctl = 0x00020000,
 263         .grp_b0ds = 0x00000030,
 264         .grp_ctlds = 0x00000030,
 265         .grp_b1ds = 0x00000030,
 266         .grp_ddrpke = 0x00000000,
 267         .grp_ddrmode = 0x00020000,
 268         .grp_ddr_type = 0x000c0000,
 269 };
 270
 271 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 272         .dram_dqm0 = 0x00000030,
 273         .dram_dqm1 = 0x00000030,
 274         .dram_ras = 0x00000030,
 275         .dram_cas = 0x00000030,
 276         .dram_odt0 = 0x00000030,
 277         .dram_odt1 = 0x00000030,
 278         .dram_sdba2 = 0x00000000,
 279         .dram_sdclk_0 = 0x00000008,
 280         .dram_sdqs0 = 0x00000038,
 281         .dram_sdqs1 = 0x00000030,
 282         .dram_reset = 0x00000030,
 283 };
 284
 285 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 286         .p0_mpwldectrl0 = 0x00070007,
 287         .p0_mpdgctrl0 = 0x41490145,
 288         .p0_mprddlctl = 0x40404546,
 289         .p0_mpwrdlctl = 0x4040524D,
 290 };
 291
 292 struct mx6_ddr_sysinfo ddr_sysinfo = {
 293         .dsize = 0,
 294         .cs_density = 20,
 295         .ncs = 1,
 296         .cs1_mirror = 0,
 297         .rtt_wr = 2,
 298         .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
 299         .walat = 1,             /* Write additional latency */
 300         .ralat = 5,             /* Read additional latency */
 301         .mif3_mode = 3,         /* Command prediction working mode */
 302         .bi_on = 1,             /* Bank interleaving enabled */
 303         .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 304         .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 305         .ddr_type = DDR_TYPE_DDR3,
 306 };
 307
 308 static struct mx6_ddr3_cfg mem_ddr = {
 309         .mem_speed = 800,
 310         .density = 4,
 311         .width = 16,
 312         .banks = 8,
 313         .rowaddr = 15,
 314         .coladdr = 10,
 315         .pagesz = 2,
 316         .trcd = 1375,
 317         .trcmin = 4875,
 318         .trasmin = 3500,
 319 };
 320
 321 static void ccgr_init(void)
 322 {
 323         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 324
 325         writel(0x00c03f3f, &ccm->CCGR0);
 326         writel(0xfcffff00, &ccm->CCGR1);
 327         writel(0x0cffffcc, &ccm->CCGR2);
 328         writel(0x3f3c3030, &ccm->CCGR3);
 329         writel(0xff00fffc, &ccm->CCGR4);
 330         writel(0x033f30ff, &ccm->CCGR5);
 331         writel(0x00c00fff, &ccm->CCGR6);
 332 }
 333
 334 static void spl_dram_init(void)
 335 {
 336         mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 337         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 338 }
 339
 340 void board_init_f(ulong dummy)
 341 {
 342         /* setup AIPS and disable watchdog */
 343         arch_cpu_init();
 344
 345         ccgr_init();
 346
 347         /* iomux and setup of i2c */
 348         board_early_init_f();
 349
 350         /* setup GP timer */
 351         timer_init();
 352
 353         /* UART clocks enabled and gd valid - init serial console */
 354         preloader_console_init();
 355
 356         /* DDR initialization */
 357         spl_dram_init();
 358
 359         /* Clear the BSS. */
 360         memset(__bss_start, 0, __bss_end - __bss_start);
 361
 362         /* load/boot image from boot device */
 363         board_init_r(NULL, 0);
 364 }
 365 #endif /* CONFIG_SPL_BUILD */