board/ep82xxm/ep82xxm.c

   1 /*
   2  * Copyright (C) 2006 Embedded Planet, LLC.
   3  *
   4  * Support for Embedded Planet EP82xxM boards.
   5  * Tested on EP82xxM (MPC8270).
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <mpc8260.h>
  28 #include <ioports.h>
  29 #include <asm/m8260_pci.h>
  30 #ifdef CONFIG_PCI
  31 #include <pci.h>
  32 #endif
  33 #include <miiphy.h>
  34
  35 /*
  36  * I/O Port configuration table
  37  *
  38  * if conf is 1, then that port pin will be configured at boot time
  39  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  40  */
  41
  42 #define CONFIG_SYS_FCC2 1
  43 #define CONFIG_SYS_FCC3 1
  44
  45 const iop_conf_t iop_conf_tab[4][32] = {
  46
  47     /* Port A */
  48     {   /*           conf      ppar psor pdir podr pdat */
  49         /* PA31 */ { 0,          0,   0,   0,   0,   1 }, /* PA31            */
  50         /* PA30 */ { 0,          0,   0,   0,   0,   1 }, /* PA30            */
  51         /* PA29 */ { 0,          0,   0,   0,   0,   1 }, /* PA29            */
  52         /* PA28 */ { 0,          0,   0,   0,   0,   1 }, /* PA28            */
  53         /* PA27 */ { 0,          0,   0,   0,   0,   1 }, /* PA27            */
  54         /* PA26 */ { 0,          0,   0,   0,   0,   1 }, /* PA26            */
  55         /* PA25 */ { 0,          0,   0,   0,   0,   1 }, /* PA25            */
  56         /* PA24 */ { 0,          0,   0,   0,   0,   1 }, /* PA24            */
  57         /* PA23 */ { 0,          0,   0,   0,   0,   1 }, /* PA23            */
  58         /* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22            */
  59         /* PA21 */ { 0,          0,   0,   0,   0,   1 }, /* PA21            */
  60         /* PA20 */ { 0,          0,   0,   0,   0,   1 }, /* PA20            */
  61         /* PA19 */ { 0,          0,   0,   0,   0,   1 }, /* PA19            */
  62         /* PA18 */ { 0,          0,   0,   0,   0,   1 }, /* PA18            */
  63         /* PA17 */ { 0,          0,   0,   0,   0,   1 }, /* PA17            */
  64         /* PA16 */ { 0,          0,   0,   0,   0,   1 }, /* PA16            */
  65         /* PA15 */ { 0,          0,   0,   0,   0,   1 }, /* PA15            */
  66         /* PA14 */ { 0,          0,   0,   0,   0,   1 }, /* PA14            */
  67         /* PA13 */ { 0,          0,   0,   0,   0,   1 }, /* PA13            */
  68         /* PA12 */ { 0,          0,   0,   0,   0,   1 }, /* PA12            */
  69         /* PA11 */ { 0,          0,   0,   0,   0,   1 }, /* PA11            */
  70         /* PA10 */ { 0,          0,   0,   0,   0,   1 }, /* PA10            */
  71         /* PA9  */ { 1,          1,   0,   1,   0,   1 }, /* SMC2 TxD        */
  72         /* PA8  */ { 1,          1,   0,   0,   0,   1 }, /* SMC2 RxD        */
  73         /* PA7  */ { 0,          0,   0,   0,   0,   1 }, /* PA7             */
  74         /* PA6  */ { 0,          0,   0,   0,   0,   1 }, /* PA6             */
  75         /* PA5  */ { 0,          0,   0,   0,   0,   1 }, /* PA5             */
  76         /* PA4  */ { 0,          0,   0,   0,   0,   1 }, /* PA4             */
  77         /* PA3  */ { 0,          0,   0,   0,   0,   1 }, /* PA3             */
  78         /* PA2  */ { 0,          0,   0,   0,   0,   1 }, /* PA2             */
  79         /* PA1  */ { 0,          0,   0,   0,   0,   1 }, /* PA1             */
  80         /* PA0  */ { 0,          0,   0,   0,   0,   1 }  /* PA0             */
  81     },
  82
  83     /* Port B */
  84     {   /*           conf       ppar psor pdir podr pdat */
  85         /* PB31 */ { CONFIG_SYS_FCC2,    1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
  86         /* PB30 */ { CONFIG_SYS_FCC2,    1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
  87         /* PB29 */ { CONFIG_SYS_FCC2,    1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
  88         /* PB28 */ { CONFIG_SYS_FCC2,    1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
  89         /* PB27 */ { CONFIG_SYS_FCC2,    1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
  90         /* PB26 */ { CONFIG_SYS_FCC2,    1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
  91         /* PB25 */ { CONFIG_SYS_FCC2,    1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
  92         /* PB24 */ { CONFIG_SYS_FCC2,    1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
  93         /* PB23 */ { CONFIG_SYS_FCC2,    1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
  94         /* PB22 */ { CONFIG_SYS_FCC2,    1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
  95         /* PB21 */ { CONFIG_SYS_FCC2,    1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
  96         /* PB20 */ { CONFIG_SYS_FCC2,    1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
  97         /* PB19 */ { CONFIG_SYS_FCC2,    1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
  98         /* PB18 */ { CONFIG_SYS_FCC2,    1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
  99         /* PB17 */ { CONFIG_SYS_FCC3,    1,   0,   0,   0,   0 }, /* FCC3:RX_DIV     */
 100         /* PB16 */ { CONFIG_SYS_FCC3,    1,   0,   0,   0,   0 }, /* FCC3:RX_ERR     */
 101         /* PB15 */ { CONFIG_SYS_FCC3,    1,   0,   1,   0,   0 }, /* FCC3:TX_ERR     */
 102         /* PB14 */ { CONFIG_SYS_FCC3,    1,   0,   1,   0,   0 }, /* FCC3:TX_EN      */
 103         /* PB13 */ { CONFIG_SYS_FCC3,    1,   0,   0,   0,   0 }, /* FCC3:COL        */
 104         /* PB12 */ { CONFIG_SYS_FCC3,    1,   0,   0,   0,   0 }, /* FCC3:CRS        */
 105         /* PB11 */ { CONFIG_SYS_FCC3,    1,   0,   0,   0,   0 }, /* FCC3:RXD        */
 106         /* PB10 */ { CONFIG_SYS_FCC3,    1,   0,   0,   0,   0 }, /* FCC3:RXD        */
 107         /* PB9  */ { CONFIG_SYS_FCC3,    1,   0,   0,   0,   0 }, /* FCC3:RXD        */
 108         /* PB8  */ { CONFIG_SYS_FCC3,    1,   0,   0,   0,   0 }, /* FCC3:RXD        */
 109         /* PB7  */ { 0,          0,   0,   0,   0,   0 }, /* PB7             */
 110         /* PB6  */ { CONFIG_SYS_FCC3,    1,   0,   1,   0,   0 }, /* FCC3:TXD        */
 111         /* PB5  */ { CONFIG_SYS_FCC3,    1,   0,   1,   0,   0 }, /* FCC3:TXD        */
 112         /* PB4  */ { CONFIG_SYS_FCC3,    1,   0,   1,   0,   0 }, /* FCC3:TXD        */
 113         /* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 114         /* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 115         /* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 116         /* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
 117     },
 118
 119     /* Port C */
 120     {   /*           conf       ppar psor pdir podr pdat */
 121         /* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31            */
 122         /* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30            */
 123         /* PC29 */ { 1,          1,   1,   0,   0,   0 }, /* SCC1 CTS#       */
 124         /* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28            */
 125         /* PC27 */ { CONFIG_SYS_FCC3,    1,   0,   1,   0,   0 }, /* FCC3: TXD[0]    */
 126         /* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26            */
 127         /* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25            */
 128         /* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24            */
 129         /* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
 130         /* PC22 */ { 0,          0,   0,   0,   0,   0 }, /* PC22            */
 131         /* PC21 */ { 0,          0,   0,   0,   0,   0 }, /* PC21            */
 132         /* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20            */
 133         /* PC19 */ { CONFIG_SYS_FCC2,    1,   0,   0,   0,   0 }, /* RxClk (CLK13)   */
 134         /* PC18 */ { CONFIG_SYS_FCC2,    1,   0,   0,   0,   0 }, /* TxClk (CLK14)   */
 135         /* PC17 */ { CONFIG_SYS_FCC3,    1,   0,   0,   0,   0 }, /* RxClk (CLK15)   */
 136         /* PC16 */ { CONFIG_SYS_FCC3,    1,   0,   0,   0,   0 }, /* TxClk (CLK16)   */
 137         /* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15            */
 138         /* PC14 */ { 1,          1,   0,   0,   0,   0 }, /* SCC1 CD#        */
 139         /* PC13 */ { 1,          1,   0,   0,   0,   0 }, /* SCC2 CTS#       */
 140         /* PC12 */ { 1,          1,   0,   0,   0,   0 }, /* SCC2 CD#        */
 141         /* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11            */
 142         /* PC10 */ { 1,          1,   0,   0,   0,   0 }, /* SCC3 CD#        */
 143         /* PC9  */ { 0,          0,   0,   0,   0,   0 }, /* PC9             */
 144         /* PC8  */ { 1,          1,   1,   0,   0,   0 }, /* SCC3 CTS#       */
 145         /* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7             */
 146         /* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6             */
 147         /* PC5  */ { 0,          0,   0,   0,   0,   0 }, /* PC5             */
 148         /* PC4  */ { 0,          0,   0,   0,   0,   0 }, /* PC4             */
 149         /* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3             */
 150         /* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2             */
 151         /* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1             */
 152         /* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0             */
 153     },
 154
 155     /* Port D */
 156     {   /*           conf      ppar psor pdir podr pdat */
 157         /* PD31 */ { 1,          1,   0,   0,   0,   0 }, /* SCC1 RXD        */
 158         /* PD30 */ { 1,          1,   1,   1,   0,   1 }, /* SCC1 TXD        */
 159         /* PD29 */ { 1,          1,   0,   1,   0,   0 }, /* SCC1 RTS#       */
 160         /* PD28 */ { 1,          1,   0,   0,   0,   0 }, /* SCC2 RXD        */
 161         /* PD27 */ { 1,          1,   0,   1,   0,   0 }, /* SCC2 TXD        */
 162         /* PD26 */ { 1,          1,   0,   1,   0,   0 }, /* SCC2 RTS#       */
 163         /* PD25 */ { 1,          1,   0,   0,   0,   0 }, /* SCC3 RXD        */
 164         /* PD24 */ { 1,          1,   0,   1,   0,   0 }, /* SCC3 TXD        */
 165         /* PD23 */ { 1,          1,   0,   1,   0,   0 }, /* SCC3 RTS#       */
 166         /* PD22 */ { 0,          0,   0,   0,   0,   1 }, /* PD22            */
 167         /* PD21 */ { 0,          0,   0,   0,   0,   1 }, /* PD21            */
 168         /* PD20 */ { 0,          0,   0,   0,   0,   1 }, /* PD20            */
 169         /* PD19 */ { 0,          0,   0,   0,   0,   1 }, /* PD19            */
 170         /* PD18 */ { 0,          0,   0,   0,   0,   1 }, /* PD18            */
 171         /* PD17 */ { 0,          0,   0,   0,   0,   1 }, /* PD17            */
 172         /* PD16 */ { 0,          0,   0,   0,   0,   1 }, /* PD16            */
 173         /* PD15 */ { 1,          1,   1,   0,   1,   1 }, /* I2C SDA         */
 174         /* PD14 */ { 1,          1,   1,   0,   1,   1 }, /* I2C SCL         */
 175         /* PD13 */ { 0,          0,   0,   0,   0,   1 }, /* PD13            */
 176         /* PD12 */ { 0,          0,   0,   0,   0,   1 }, /* PD12            */
 177         /* PD11 */ { 0,          0,   0,   0,   0,   1 }, /* PD11            */
 178         /* PD10 */ { 0,          0,   0,   0,   0,   1 }, /* PD10            */
 179         /* PD9  */ { 1,          1,   0,   1,   0,   1 }, /* SMC1 TxD        */
 180         /* PD8  */ { 1,          1,   0,   0,   0,   1 }, /* SMC1 RxD        */
 181         /* PD7  */ { 1,          1,   0,   0,   0,   1 }, /* SMC1 SMSYN      */
 182         /* PD6  */ { 0,          0,   0,   0,   0,   1 }, /* PD6             */
 183         /* PD5  */ { 0,          0,   0,   0,   0,   1 }, /* PD5             */
 184         /* PD4  */ { 0,          0,   0,   0,   0,   1 }, /* PD4             */
 185         /* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 186         /* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 187         /* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 188         /* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
 189     }
 190 };
 191
 192 #ifdef CONFIG_PCI
 193 typedef struct pci_ic_s {
 194         unsigned long pci_int_stat;
 195         unsigned long pci_int_mask;
 196 }pci_ic_t;
 197 #endif
 198
 199 int board_early_init_f (void)
 200 {
 201         vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
 202
 203         bcsr[4] |= 0x30; /* Turn the LEDs off */
 204
 205 #if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
 206         bcsr[6] |= 0x10;
 207 #endif
 208 #if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
 209         bcsr[7] |= 0x10;
 210 #endif
 211
 212 #if CONFIG_SYS_FCC3
 213         bcsr[8] |= 0xC0;
 214 #endif /* CONFIG_SYS_FCC3 */
 215 #if CONFIG_SYS_FCC2
 216         bcsr[8] |= 0x30;
 217 #endif /* CONFIG_SYS_FCC2 */
 218
 219         return 0;
 220 }
 221
 222 phys_size_t initdram(int board_type)
 223 {
 224         /* Size in MB of SDRAM populated on board*/
 225         long int msize = 256;
 226
 227 #ifndef CONFIG_SYS_RAMBOOT
 228         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 229         volatile memctl8260_t *memctl = &immap->im_memctl;
 230         uint psdmr = CONFIG_SYS_PSDMR;
 231         int i;
 232
 233         unsigned char   ramtmp;
 234         unsigned char   *ramptr1 = (unsigned char *)0x00000110;
 235
 236         memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 237
 238 udelay(400);
 239
 240         /* Initialise 60x bus SDRAM */
 241         memctl->memc_psrt = CONFIG_SYS_PSRT;
 242         memctl->memc_or1  = CONFIG_SYS_SDRAM_OR;
 243         memctl->memc_br1  = CONFIG_SYS_SDRAM_BR;
 244         memctl->memc_psdmr = psdmr;
 245
 246 udelay(400);
 247
 248         memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
 249         ramtmp = *ramptr1;
 250         memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
 251         for (i = 0; i < 8; i++) {
 252                 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
 253         }
 254         ramtmp = *ramptr1;
 255         memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
 256         *ramptr1  = 0xFF;
 257         memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
 258 #endif /* !CONFIG_SYS_RAMBOOT */
 259
 260         /* Return total 60x bus SDRAM size */
 261         return msize * 1024 * 1024;
 262 }
 263
 264 int checkboard(void)
 265 {
 266         vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
 267
 268         puts("Board: ");
 269         switch (bcsr[0]) {
 270         case 0x0A:
 271                 printf("EP82xxM 1.0 CPLD revision %d\n", bcsr[1]);
 272                 break;
 273         default:
 274                 printf("unknown: ID=%02X\n", bcsr[0]);
 275         }
 276
 277         return 0;
 278 }
 279
 280 #ifdef CONFIG_PCI
 281 struct pci_controller hose;
 282
 283 extern void pci_mpc8250_init(struct pci_controller *);
 284
 285 void pci_init_board(void)
 286 {
 287         pci_mpc8250_init(&hose);
 288 }
 289 #endif