board/esd/apc405/apc405.c

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <command.h>
  27 #include <malloc.h>
  28
  29 /* ------------------------------------------------------------------------- */
  30
  31 #if 0
  32 #define FPGA_DEBUG
  33 #endif
  34
  35 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
  36 extern void lxt971_no_sleep(void);
  37
  38 /* fpga configuration data - gzip compressed and generated by bin2c */
  39 const unsigned char fpgadata[] =
  40 {
  41 #include "fpgadata.c"
  42 };
  43
  44 /*
  45  * include common fpga code (for esd boards)
  46  */
  47 #include "../common/fpga.c"
  48
  49
  50 /* Prototypes */
  51 int gunzip(void *, int, unsigned char *, unsigned long *);
  52
  53
  54 #ifdef CONFIG_LCD_USED
  55 /* logo bitmap data - gzip compressed and generated by bin2c */
  56 unsigned char logo_bmp[] =
  57 {
  58 #include CFG_LCD_LOGO_NAME
  59 };
  60
  61 /*
  62  * include common lcd code (for esd boards)
  63  */
  64 #include "../common/lcd.c"
  65
  66 #include CFG_LCD_HEADER_NAME
  67 #endif /* CONFIG_LCD_USED */
  68
  69
  70 int board_revision(void)
  71 {
  72         unsigned long cntrl0Reg;
  73         unsigned long value;
  74
  75         /*
  76          * Get version of APC405 board from GPIO's
  77          */
  78
  79         /*
  80          * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
  81          */
  82         cntrl0Reg = mfdcr(cntrl0);
  83         mtdcr(cntrl0, cntrl0Reg | 0x03000000);
  84         out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
  85         out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
  86         udelay(1000);                   /* wait some time before reading input */
  87         value = in32(GPIO0_IR) & 0x00180000;       /* get config bits */
  88
  89         /*
  90          * Restore GPIO settings
  91          */
  92         mtdcr(cntrl0, cntrl0Reg);
  93
  94         switch (value) {
  95         case 0x00180000:
  96                 /* CS2==1 && CS3==1 -> version <= 1.2 */
  97                 return 2;
  98         case 0x00080000:
  99                 /* CS2==0 && CS3==1 -> version 1.3 */
 100                 return 3;
 101 #if 0 /* not yet manufactured ! */
 102         case 0x00100000:
 103                 /* CS2==1 && CS3==0 -> version 1.4 */
 104                 return 4;
 105         case 0x00000000:
 106                 /* CS2==0 && CS3==0 -> version 1.5 */
 107                 return 5;
 108 #endif
 109         default:
 110                 /* should not be reached! */
 111                 return 0;
 112         }
 113 }
 114
 115
 116 int board_early_init_f (void)
 117 {
 118         /*
 119          * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
 120          */
 121         out32(GPIO0_ODR, 0x00000000);        /* no open drain pins      */
 122         out32(GPIO0_TCR, CFG_FPGA_PRG);      /* setup for output        */
 123         out32(GPIO0_OR,  CFG_FPGA_PRG);      /* set output pins to high */
 124         out32(GPIO0_OR, 0);                  /* pull prg low            */
 125
 126         /*
 127          * IRQ 0-15  405GP internally generated; active high; level sensitive
 128          * IRQ 16    405GP internally generated; active low; level sensitive
 129          * IRQ 17-24 RESERVED
 130          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
 131          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
 132          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
 133          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
 134          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
 135          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 136          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 137          */
 138         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 139         mtdcr(uicer, 0x00000000);       /* disable all ints */
 140         mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
 141         mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
 142         mtdcr(uictr, 0x10000000);       /* set int trigger levels */
 143         mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
 144         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 145
 146         /*
 147          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
 148          */
 149 #if 1 /* test-only */
 150         mtebc (epcr, 0xa8400000); /* ebc always driven */
 151 #else
 152         mtebc (epcr, 0x28400000); /* ebc in high-z */
 153 #endif
 154
 155         return 0;
 156 }
 157
 158
 159 /* ------------------------------------------------------------------------- */
 160
 161 int misc_init_f (void)
 162 {
 163         return 0;  /* dummy implementation */
 164 }
 165
 166
 167 int misc_init_r (void)
 168 {
 169         DECLARE_GLOBAL_DATA_PTR;
 170
 171         volatile unsigned short *fpga_mode =
 172                 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
 173         volatile unsigned short *fpga_ctrl2 =
 174                 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2);
 175         volatile unsigned char *duart0_mcr =
 176                 (unsigned char *)((ulong)DUART0_BA + 4);
 177         volatile unsigned char *duart1_mcr =
 178                 (unsigned char *)((ulong)DUART1_BA + 4);
 179         volatile unsigned short *fuji_lcdbl_pwm =
 180                 (unsigned short *)((ulong)0xf0100200 + 0xa0);
 181         unsigned char *dst;
 182         ulong len = sizeof(fpgadata);
 183         int status;
 184         int index;
 185         int i;
 186         unsigned long cntrl0Reg;
 187
 188         /*
 189          * Setup GPIO pins (CS6+CS7 as GPIO)
 190          */
 191         cntrl0Reg = mfdcr(cntrl0);
 192         mtdcr(cntrl0, cntrl0Reg | 0x00300000);
 193
 194         dst = malloc(CFG_FPGA_MAX_SIZE);
 195         if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 196                 printf ("GUNZIP ERROR - must RESET board to recover\n");
 197                 do_reset (NULL, 0, 0, NULL);
 198         }
 199
 200         status = fpga_boot(dst, len);
 201         if (status != 0) {
 202                 printf("\nFPGA: Booting failed ");
 203                 switch (status) {
 204                 case ERROR_FPGA_PRG_INIT_LOW:
 205                         printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
 206                         break;
 207                 case ERROR_FPGA_PRG_INIT_HIGH:
 208                         printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
 209                         break;
 210                 case ERROR_FPGA_PRG_DONE:
 211                         printf("(Timeout: DONE not high after programming FPGA)\n ");
 212                         break;
 213                 }
 214
 215                 /* display infos on fpgaimage */
 216                 index = 15;
 217                 for (i=0; i<4; i++) {
 218                         len = dst[index];
 219                         printf("FPGA: %s\n", &(dst[index+1]));
 220                         index += len+3;
 221                 }
 222                 putc ('\n');
 223                 /* delayed reboot */
 224                 for (i=20; i>0; i--) {
 225                         printf("Rebooting in %2d seconds \r",i);
 226                         for (index=0;index<1000;index++)
 227                                 udelay(1000);
 228                 }
 229                 putc ('\n');
 230                 do_reset(NULL, 0, 0, NULL);
 231         }
 232
 233         /* restore gpio/cs settings */
 234         mtdcr(cntrl0, cntrl0Reg);
 235
 236         puts("FPGA:  ");
 237
 238         /* display infos on fpgaimage */
 239         index = 15;
 240         for (i=0; i<4; i++) {
 241                 len = dst[index];
 242                 printf("%s ", &(dst[index+1]));
 243                 index += len+3;
 244         }
 245         putc ('\n');
 246
 247         free(dst);
 248
 249         /*
 250          * Reset FPGA via FPGA_DATA pin
 251          */
 252         SET_FPGA(FPGA_PRG | FPGA_CLK);
 253         udelay(1000); /* wait 1ms */
 254         SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 255         udelay(1000); /* wait 1ms */
 256
 257         /*
 258          * Write board revision in FPGA
 259          */
 260         *fpga_ctrl2 = (*fpga_ctrl2 & 0xfff0) | (gd->board_type & 0x000f);
 261
 262         /*
 263          * Enable power on PS/2 interface (with reset)
 264          */
 265         *fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;
 266         for (i=0;i<100;i++)
 267                 udelay(1000);
 268         udelay(1000);
 269         *fpga_mode &= ~CFG_FPGA_CTRL_PS2_RESET;
 270
 271         /*
 272          * Enable interrupts in exar duart mcr[3]
 273          */
 274         *duart0_mcr = 0x08;
 275         *duart1_mcr = 0x08;
 276
 277         /*
 278          * Init lcd interface and display logo
 279          */
 280         lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
 281                  regs_13806_640_480_16bpp,
 282                  sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
 283                  logo_bmp, sizeof(logo_bmp));
 284
 285         /*
 286          * Reset microcontroller and setup backlight PWM controller
 287          */
 288         *fpga_mode |= 0x0014;
 289         for (i=0;i<10;i++)
 290                 udelay(1000);
 291         *fpga_mode |= 0x001c;
 292         *fuji_lcdbl_pwm = 0x00ff;
 293
 294         return (0);
 295 }
 296
 297
 298 /*
 299  * Check Board Identity:
 300  */
 301
 302 int checkboard (void)
 303 {
 304         DECLARE_GLOBAL_DATA_PTR;
 305
 306         unsigned char str[64];
 307         int i = getenv_r ("serial#", str, sizeof(str));
 308
 309         puts ("Board: ");
 310
 311         if (i == -1) {
 312                 puts ("### No HW ID - assuming APC405");
 313         } else {
 314                 puts(str);
 315         }
 316
 317         gd->board_type = board_revision();
 318         printf(", Rev 1.%ld\n", gd->board_type);
 319
 320         /*
 321          * Disable sleep mode in LXT971
 322          */
 323         lxt971_no_sleep();
 324
 325         return 0;
 326 }
 327
 328 /* ------------------------------------------------------------------------- */
 329
 330 long int initdram (int board_type)
 331 {
 332         unsigned long val;
 333
 334         mtdcr(memcfga, mem_mb0cf);
 335         val = mfdcr(memcfgd);
 336
 337 #if 0
 338         printf("\nmb0cf=%x\n", val); /* test-only */
 339         printf("strap=%x\n", mfdcr(strap)); /* test-only */
 340 #endif
 341
 342         return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 343 }
 344
 345 /* ------------------------------------------------------------------------- */
 346
 347 int testdram (void)
 348 {
 349         /* TODO: XXX XXX XXX */
 350         printf ("test: 16 MB - ok\n");
 351
 352         return (0);
 353 }
 354
 355 /* ------------------------------------------------------------------------- */
 356
 357 #ifdef CONFIG_IDE_RESET
 358
 359 void ide_set_reset(int on)
 360 {
 361         volatile unsigned short *fpga_mode =
 362                 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
 363
 364         /*
 365          * Assert or deassert CompactFlash Reset Pin
 366          */
 367         if (on) {               /* assert RESET */
 368                 *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
 369         } else {                /* release RESET */
 370                 *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
 371         }
 372 }
 373
 374 #endif /* CONFIG_IDE_RESET */
 375
 376 /* ------------------------------------------------------------------------- */