board/esd/apc405/apc405.c

   1 /*
   2  * (C) Copyright 2005-2008
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4  *
   5  * (C) Copyright 2001-2003
   6  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/processor.h>
  13 #include <asm/io.h>
  14 #include <command.h>
  15 #include <malloc.h>
  16 #include <flash.h>
  17 #include <mtd/cfi_flash.h>
  18 #include <asm/4xx_pci.h>
  19 #include <pci.h>
  20 #include <usb.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #undef FPGA_DEBUG
  25
  26 extern void lxt971_no_sleep(void);
  27
  28 /* fpga configuration data - gzip compressed and generated by bin2c */
  29 const unsigned char fpgadata[] =
  30 {
  31 #include "fpgadata.c"
  32 };
  33
  34 /*
  35  * include common fpga code (for esd boards)
  36  */
  37 #include "../common/fpga.c"
  38
  39 #ifdef CONFIG_LCD_USED
  40 /* logo bitmap data - gzip compressed and generated by bin2c */
  41 unsigned char logo_bmp[] =
  42 {
  43 #include "logo_640_480_24bpp.c"
  44 };
  45
  46 /*
  47  * include common lcd code (for esd boards)
  48  */
  49 #include "../common/lcd.c"
  50 #include "../common/s1d13505_640_480_16bpp.h"
  51 #include "../common/s1d13806_640_480_16bpp.h"
  52 #endif /* CONFIG_LCD_USED */
  53
  54 /*
  55  * include common auto-update code (for esd boards)
  56  */
  57 #include "../common/auto_update.h"
  58
  59 au_image_t au_image[] = {
  60         {"preinst.img", 0, -1, AU_SCRIPT},
  61         {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
  62         {"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
  63         {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
  64         {"work.img", 0xfe500000, 0x01400000, AU_NOR},
  65         {"data.img", 0xff900000, 0x00580000, AU_NOR},
  66         {"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
  67         {"postinst.img", 0, 0, AU_SCRIPT},
  68 };
  69
  70 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
  71
  72 int board_revision(void)
  73 {
  74         unsigned long CPC0_CR0Reg;
  75         unsigned long value;
  76
  77         /*
  78          * Get version of APC405 board from GPIO's
  79          */
  80
  81         /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
  82         CPC0_CR0Reg = mfdcr(CPC0_CR0);
  83         mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
  84         out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
  85         out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
  86
  87         /* wait some time before reading input */
  88         udelay(1000);
  89
  90         /* get config bits */
  91         value = in_be32((void*)GPIO0_IR) & 0x001c0000;
  92         /*
  93          * Restore GPIO settings
  94          */
  95         mtdcr(CPC0_CR0, CPC0_CR0Reg);
  96
  97         switch (value) {
  98         case 0x001c0000:
  99                 /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
 100                 return 2;
 101         case 0x000c0000:
 102                 /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
 103                 return 3;
 104         case 0x00180000:
 105                 /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
 106                 return 6;
 107         case 0x00140000:
 108                 /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
 109                 return 8;
 110         default:
 111                 /* should not be reached! */
 112                 return 0;
 113         }
 114 }
 115
 116 int board_early_init_f (void)
 117 {
 118         /*
 119          * First pull fpga-prg pin low, to disable fpga logic
 120          */
 121         out_be32((void*)GPIO0_ODR, 0x00000000);        /* no open drain pins */
 122         out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output   */
 123         out_be32((void*)GPIO0_OR, 0);                  /* pull prg low       */
 124
 125         /*
 126          * IRQ 0-15  405GP internally generated; active high; level sensitive
 127          * IRQ 16    405GP internally generated; active low; level sensitive
 128          * IRQ 17-24 RESERVED
 129          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
 130          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
 131          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
 132          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
 133          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
 134          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 135          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 136          */
 137         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 138         mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
 139         mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
 140         mtdcr(UIC0PR, 0xFFFFFF81);       /* set int polarities */
 141         mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
 142         mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0 */
 143         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 144
 145         /*
 146          * EBC Configuration Register: set ready timeout to 512 ebc-clks
 147          */
 148         mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
 149
 150         /*
 151          * New boards have a single 32MB flash connected to CS0
 152          * instead of two 16MB flashes on CS0+1.
 153          */
 154         if (board_revision() >= 8) {
 155                 /* disable CS1 */
 156                 mtebc(PB1AP, 0);
 157                 mtebc(PB1CR, 0);
 158
 159                 /* resize CS0 to 32MB */
 160                 mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
 161                 mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
 162         }
 163
 164         return 0;
 165 }
 166
 167 int board_early_init_r(void)
 168 {
 169         if (gd->board_type >= 8)
 170                 cfi_flash_num_flash_banks = 1;
 171
 172         return 0;
 173 }
 174
 175 #define FUJI_BASE    0xf0100200
 176 #define LCDBL_PWM    0xa0
 177 #define LCDBL_PWMMIN 0xa4
 178 #define LCDBL_PWMMAX 0xa8
 179
 180 int misc_init_r(void)
 181 {
 182         u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
 183         u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
 184         u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
 185         u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
 186         unsigned char *dst;
 187         ulong len = sizeof(fpgadata);
 188         int status;
 189         int index;
 190         int i;
 191         unsigned long CPC0_CR0Reg;
 192         char *str;
 193         uchar *logo_addr;
 194         ulong logo_size;
 195         ushort minb, maxb;
 196         int result;
 197
 198         /*
 199          * Setup GPIO pins (CS6+CS7 as GPIO)
 200          */
 201         CPC0_CR0Reg = mfdcr(CPC0_CR0);
 202         mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
 203
 204         dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
 205         if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 206                 printf("GUNZIP ERROR - must RESET board to recover\n");
 207                 do_reset(NULL, 0, 0, NULL);
 208         }
 209
 210         status = fpga_boot(dst, len);
 211         if (status != 0) {
 212                 printf("\nFPGA: Booting failed ");
 213                 switch (status) {
 214                 case ERROR_FPGA_PRG_INIT_LOW:
 215                         printf("(Timeout: "
 216                                "INIT not low after asserting PROGRAM*)\n ");
 217                         break;
 218                 case ERROR_FPGA_PRG_INIT_HIGH:
 219                         printf("(Timeout: "
 220                                "INIT not high after deasserting PROGRAM*)\n ");
 221                         break;
 222                 case ERROR_FPGA_PRG_DONE:
 223                         printf("(Timeout: "
 224                                "DONE not high after programming FPGA)\n ");
 225                         break;
 226                 }
 227
 228                 /* display infos on fpgaimage */
 229                 index = 15;
 230                 for (i = 0; i < 4; i++) {
 231                         len = dst[index];
 232                         printf("FPGA: %s\n", &(dst[index+1]));
 233                         index += len + 3;
 234                 }
 235                 putc('\n');
 236                 /* delayed reboot */
 237                 for (i = 20; i > 0; i--) {
 238                         printf("Rebooting in %2d seconds \r",i);
 239                         for (index = 0; index < 1000; index++)
 240                                 udelay(1000);
 241                 }
 242                 putc('\n');
 243                 do_reset(NULL, 0, 0, NULL);
 244         }
 245
 246         /* restore gpio/cs settings */
 247         mtdcr(CPC0_CR0, CPC0_CR0Reg);
 248
 249         puts("FPGA:  ");
 250
 251         /* display infos on fpgaimage */
 252         index = 15;
 253         for (i = 0; i < 4; i++) {
 254                 len = dst[index];
 255                 printf("%s ", &(dst[index + 1]));
 256                 index += len + 3;
 257         }
 258         putc('\n');
 259
 260         free(dst);
 261
 262         /*
 263          * Reset FPGA via FPGA_DATA pin
 264          */
 265         SET_FPGA(FPGA_PRG | FPGA_CLK);
 266         udelay(1000); /* wait 1ms */
 267         SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 268         udelay(1000); /* wait 1ms */
 269
 270         /*
 271          * Write board revision in FPGA
 272          */
 273         out_be16(fpga_ctrl2,
 274                  (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
 275
 276         /*
 277          * Enable power on PS/2 interface (with reset)
 278          */
 279         out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
 280         for (i=0;i<100;i++)
 281                 udelay(1000);
 282         udelay(1000);
 283         out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
 284
 285         /*
 286          * Enable interrupts in exar duart mcr[3]
 287          */
 288         out_8(duart0_mcr, 0x08);
 289         out_8(duart1_mcr, 0x08);
 290
 291         /*
 292          * Init lcd interface and display logo
 293          */
 294         str = getenv("splashimage");
 295         if (str) {
 296                 logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
 297                 logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
 298         } else {
 299                 logo_addr = logo_bmp;
 300                 logo_size = sizeof(logo_bmp);
 301         }
 302
 303         if (gd->board_type >= 6) {
 304                 result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
 305                                   (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 306                                   regs_13505_640_480_16bpp,
 307                                   sizeof(regs_13505_640_480_16bpp) /
 308                                   sizeof(regs_13505_640_480_16bpp[0]),
 309                                   logo_addr, logo_size);
 310                 if (result && str) {
 311                         /* retry with internal image */
 312                         logo_addr = logo_bmp;
 313                         logo_size = sizeof(logo_bmp);
 314                         lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
 315                                  (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 316                                  regs_13505_640_480_16bpp,
 317                                  sizeof(regs_13505_640_480_16bpp) /
 318                                  sizeof(regs_13505_640_480_16bpp[0]),
 319                                  logo_addr, logo_size);
 320                 }
 321         } else {
 322                 result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
 323                                   (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 324                                   regs_13806_640_480_16bpp,
 325                                   sizeof(regs_13806_640_480_16bpp) /
 326                                   sizeof(regs_13806_640_480_16bpp[0]),
 327                                   logo_addr, logo_size);
 328                 if (result && str) {
 329                         /* retry with internal image */
 330                         logo_addr = logo_bmp;
 331                         logo_size = sizeof(logo_bmp);
 332                         lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
 333                                  (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 334                                  regs_13806_640_480_16bpp,
 335                                  sizeof(regs_13806_640_480_16bpp) /
 336                                  sizeof(regs_13806_640_480_16bpp[0]),
 337                                  logo_addr, logo_size);
 338                 }
 339         }
 340
 341         /*
 342          * Reset microcontroller and setup backlight PWM controller
 343          */
 344         out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
 345         for (i=0;i<10;i++)
 346                 udelay(1000);
 347         out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
 348
 349         minb = 0;
 350         maxb = 0xff;
 351         str = getenv("lcdbl");
 352         if (str) {
 353                 minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
 354                 if (str && (*str=',')) {
 355                         str++;
 356                         maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
 357                 } else
 358                         minb = 0;
 359
 360                 out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
 361                 out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
 362
 363                 printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
 364         }
 365         out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
 366
 367         /*
 368          * fix environment for field updated units
 369          */
 370         if (getenv("altbootcmd") == NULL) {
 371                 setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
 372                 setenv("usbargs", CONFIG_SYS_USB_ARGS);
 373                 setenv("bootcmd", CONFIG_BOOTCOMMAND);
 374                 setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
 375                 setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
 376                 setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
 377                 saveenv();
 378         }
 379
 380         return (0);
 381 }
 382
 383 /*
 384  * Check Board Identity:
 385  */
 386 int checkboard (void)
 387 {
 388         char str[64];
 389         int i = getenv_f("serial#", str, sizeof(str));
 390
 391         puts ("Board: ");
 392
 393         if (i == -1) {
 394                 puts ("### No HW ID - assuming APC405");
 395         } else {
 396                 puts(str);
 397         }
 398
 399         gd->board_type = board_revision();
 400         printf(", Rev. 1.%ld\n", gd->board_type);
 401
 402         return 0;
 403 }
 404
 405 #ifdef CONFIG_IDE_RESET
 406 void ide_set_reset(int on)
 407 {
 408         u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
 409
 410         /*
 411          * Assert or deassert CompactFlash Reset Pin
 412          */
 413         if (on) {
 414                 out_be16(fpga_mode,
 415                          in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
 416         } else {
 417                 out_be16(fpga_mode,
 418                          in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
 419         }
 420 }
 421 #endif /* CONFIG_IDE_RESET */
 422
 423 void reset_phy(void)
 424 {
 425         /*
 426          * Disable sleep mode in LXT971
 427          */
 428         lxt971_no_sleep();
 429 }
 430
 431 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
 432 int board_usb_init(int index, enum board_usb_init_type init)
 433 {
 434         return 0;
 435 }
 436
 437 int usb_board_stop(void)
 438 {
 439         unsigned short tmp;
 440         int i;
 441
 442         /*
 443          * reset PCI bus
 444          * This is required to make some very old Linux OHCI driver
 445          * work after U-Boot has used the OHCI controller.
 446          */
 447         pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
 448         pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));
 449
 450         for (i = 0; i < 100; i++)
 451                 udelay(1000);
 452
 453         pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
 454         return 0;
 455 }
 456
 457 int board_usb_cleanup(int index, enum board_usb_init_type init)
 458 {
 459         return usb_board_stop();
 460 }
 461 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */