board/esd/cpci405/cpci405.c

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <command.h>
  27 #include <malloc.h>
  28
  29 /* ------------------------------------------------------------------------- */
  30 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);       /*cmd_boot.c*/
  31 #if 0
  32 #define FPGA_DEBUG
  33 #endif
  34
  35 /* fpga configuration data - generated by bin2cc */
  36 const unsigned char fpgadata[] =
  37 {
  38 #ifdef CONFIG_CPCI405_VER2
  39 # ifdef CONFIG_CPCI405AB
  40 #  include "fpgadata_cpci405ab.c"
  41 # else
  42 #  include "fpgadata_cpci4052.c"
  43 # endif
  44 #else
  45 # include "fpgadata_cpci405.c"
  46 #endif
  47 };
  48
  49 /*
  50  * include common fpga code (for esd boards)
  51  */
  52 #include "../common/fpga.c"
  53
  54
  55 /* Prototypes */
  56 int cpci405_version(void);
  57 int gunzip(void *, int, unsigned char *, int *);
  58
  59
  60 int board_pre_init (void)
  61 {
  62 #ifndef CONFIG_CPCI405_VER2
  63         int index, len, i;
  64         int status;
  65 #endif
  66
  67 #ifdef FPGA_DEBUG
  68         DECLARE_GLOBAL_DATA_PTR;
  69
  70         /* set up serial port with default baudrate */
  71         (void) get_clocks ();
  72         gd->baudrate = CONFIG_BAUDRATE;
  73         serial_init ();
  74         console_init_f();
  75 #endif
  76
  77         /*
  78          * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
  79          */
  80         out32(GPIO0_ODR, 0x00000000);        /* no open drain pins      */
  81         out32(GPIO0_TCR, CFG_FPGA_PRG);      /* setup for output        */
  82         out32(GPIO0_OR,  CFG_FPGA_PRG);      /* set output pins to high */
  83         out32(GPIO0_OR, 0);                  /* pull prg low            */
  84
  85         /*
  86          * Boot onboard FPGA
  87          */
  88 #ifndef CONFIG_CPCI405_VER2
  89         if (cpci405_version() == 1) {
  90                 status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
  91                 if (status != 0) {
  92                         /* booting FPGA failed */
  93 #ifndef FPGA_DEBUG
  94                         DECLARE_GLOBAL_DATA_PTR;
  95
  96                         /* set up serial port with default baudrate */
  97                         (void) get_clocks ();
  98                         gd->baudrate = CONFIG_BAUDRATE;
  99                         serial_init ();
 100                         console_init_f();
 101 #endif
 102                         printf("\nFPGA: Booting failed ");
 103                         switch (status) {
 104                         case ERROR_FPGA_PRG_INIT_LOW:
 105                                 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
 106                                 break;
 107                         case ERROR_FPGA_PRG_INIT_HIGH:
 108                                 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
 109                                 break;
 110                         case ERROR_FPGA_PRG_DONE:
 111                                 printf("(Timeout: DONE not high after programming FPGA)\n ");
 112                                 break;
 113                         }
 114
 115                         /* display infos on fpgaimage */
 116                         index = 15;
 117                         for (i=0; i<4; i++) {
 118                                 len = fpgadata[index];
 119                                 printf("FPGA: %s\n", &(fpgadata[index+1]));
 120                                 index += len+3;
 121                         }
 122                         putc ('\n');
 123                         /* delayed reboot */
 124                         for (i=20; i>0; i--) {
 125                                 printf("Rebooting in %2d seconds \r",i);
 126                                 for (index=0;index<1000;index++)
 127                                         udelay(1000);
 128                         }
 129                         putc ('\n');
 130                         do_reset(NULL, 0, 0, NULL);
 131                 }
 132         }
 133 #endif /* !CONFIG_CPCI405_VER2 */
 134
 135         /*
 136          * IRQ 0-15  405GP internally generated; active high; level sensitive
 137          * IRQ 16    405GP internally generated; active low; level sensitive
 138          * IRQ 17-24 RESERVED
 139          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
 140          * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
 141          * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
 142          * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
 143          * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
 144          * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
 145          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 146          */
 147         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 148         mtdcr(uicer, 0x00000000);       /* disable all ints */
 149         mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
 150         if (cpci405_version() == 3) {
 151                 mtdcr(uicpr, 0xFFFFFF99);       /* set int polarities */
 152         } else {
 153                 mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
 154         }
 155         mtdcr(uictr, 0x10000000);       /* set int trigger levels */
 156         mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
 157         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 158
 159         return 0;
 160 }
 161
 162
 163 /* ------------------------------------------------------------------------- */
 164
 165 int ctermm2(void)
 166 {
 167 #ifdef CONFIG_CPCI405_VER2
 168         return 0;                       /* no, board is cpci405 */
 169 #else
 170         if ((*(unsigned char *)0xf0000400 == 0x00) &&
 171             (*(unsigned char *)0xf0000401 == 0x01))
 172                 return 0;               /* no, board is cpci405 */
 173         else
 174                 return -1;              /* yes, board is cterm-m2 */
 175 #endif
 176 }
 177
 178
 179 int cpci405_host(void)
 180 {
 181         if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
 182                 return -1;              /* yes, board is cpci405 host */
 183         else
 184                 return 0;               /* no, board is cpci405 adapter */
 185 }
 186
 187
 188 int cpci405_version(void)
 189 {
 190         unsigned long cntrl0Reg;
 191         unsigned long value;
 192
 193         /*
 194          * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
 195          */
 196         cntrl0Reg = mfdcr(cntrl0);
 197         mtdcr(cntrl0, cntrl0Reg | 0x03000000);
 198         out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
 199         out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
 200         udelay(1000);                   /* wait some time before reading input */
 201         value = in32(GPIO0_IR) & 0x00180000;       /* get config bits */
 202
 203         /*
 204          * Restore GPIO settings
 205          */
 206         mtdcr(cntrl0, cntrl0Reg);
 207
 208         switch (value) {
 209         case 0x00180000:
 210                 /* CS2==1 && CS3==1 -> version 1 */
 211                 return 1;
 212         case 0x00080000:
 213                 /* CS2==0 && CS3==1 -> version 2 */
 214                 return 2;
 215         case 0x00100000:
 216                 /* CS2==1 && CS3==0 -> version 3 */
 217                 return 3;
 218         case 0x00000000:
 219                 /* CS2==0 && CS3==0 -> version 4 */
 220                 return 4;
 221         default:
 222                 /* should not be reached! */
 223                 return 2;
 224         }
 225 }
 226
 227
 228 int misc_init_f (void)
 229 {
 230         return 0;  /* dummy implementation */
 231 }
 232
 233
 234 int misc_init_r (void)
 235 {
 236         DECLARE_GLOBAL_DATA_PTR;
 237
 238         bd_t *bd = gd->bd;
 239         char *  tmp;                    /* Temporary char pointer      */
 240         unsigned long cntrl0Reg;
 241
 242 #ifdef CONFIG_CPCI405_VER2
 243         unsigned char *dst;
 244         ulong len = sizeof(fpgadata);
 245         int status;
 246         int index;
 247         int i;
 248
 249         /*
 250          * On CPCI-405 version 2 the environment is saved in eeprom!
 251          * FPGA can be gzip compressed (malloc) and booted this late.
 252          */
 253
 254         if (cpci405_version() >= 2) {
 255                 /*
 256                  * Setup GPIO pins (CS6+CS7 as GPIO)
 257                  */
 258                 cntrl0Reg = mfdcr(cntrl0);
 259                 mtdcr(cntrl0, cntrl0Reg | 0x00300000);
 260
 261                 dst = malloc(CFG_FPGA_MAX_SIZE);
 262                 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
 263                         printf ("GUNZIP ERROR - must RESET board to recover\n");
 264                         do_reset (NULL, 0, 0, NULL);
 265                 }
 266
 267                 status = fpga_boot(dst, len);
 268                 if (status != 0) {
 269                         printf("\nFPGA: Booting failed ");
 270                         switch (status) {
 271                         case ERROR_FPGA_PRG_INIT_LOW:
 272                                 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
 273                                 break;
 274                         case ERROR_FPGA_PRG_INIT_HIGH:
 275                                 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
 276                                 break;
 277                         case ERROR_FPGA_PRG_DONE:
 278                                 printf("(Timeout: DONE not high after programming FPGA)\n ");
 279                                 break;
 280                         }
 281
 282                         /* display infos on fpgaimage */
 283                         index = 15;
 284                         for (i=0; i<4; i++) {
 285                                 len = dst[index];
 286                                 printf("FPGA: %s\n", &(dst[index+1]));
 287                                 index += len+3;
 288                         }
 289                         putc ('\n');
 290                         /* delayed reboot */
 291                         for (i=20; i>0; i--) {
 292                                 printf("Rebooting in %2d seconds \r",i);
 293                                 for (index=0;index<1000;index++)
 294                                         udelay(1000);
 295                         }
 296                         putc ('\n');
 297                         do_reset(NULL, 0, 0, NULL);
 298                 }
 299
 300                 /* restore gpio/cs settings */
 301                 mtdcr(cntrl0, cntrl0Reg);
 302
 303                 puts("FPGA:  ");
 304
 305                 /* display infos on fpgaimage */
 306                 index = 15;
 307                 for (i=0; i<4; i++) {
 308                         len = dst[index];
 309                         printf("%s ", &(dst[index+1]));
 310                         index += len+3;
 311                 }
 312                 putc ('\n');
 313
 314                 free(dst);
 315
 316                 /*
 317                  * Reset FPGA via FPGA_DATA pin
 318                  */
 319                 SET_FPGA(FPGA_PRG | FPGA_CLK);
 320                 udelay(1000); /* wait 1ms */
 321                 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 322                 udelay(1000); /* wait 1ms */
 323
 324                 if (cpci405_version() == 3) {
 325                         volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
 326                         volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
 327
 328                         /*
 329                          * Enable outputs in fpga on version 3 board
 330                          */
 331                         *fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT;
 332
 333                         /*
 334                          * Set outputs to 0
 335                          */
 336                         *leds = 0x00;
 337
 338                         /*
 339                          * Reset external DUART
 340                          */
 341                         *fpga_mode |= CFG_FPGA_MODE_DUART_RESET;
 342                         udelay(100);
 343                         *fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
 344                 }
 345         }
 346         else {
 347                 puts("\n*** U-Boot Version does not match Board Version!\n");
 348                 puts("*** CPCI-405 Version 1.x detected!\n");
 349                 puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
 350         }
 351
 352 #else /* CONFIG_CPCI405_VER2 */
 353
 354         /*
 355          * Generate last byte of ip-addr from code-plug @ 0xf0000400
 356          */
 357         if (ctermm2()) {
 358                 char str[32];
 359                 unsigned char ipbyte = *(unsigned char *)0xf0000400;
 360
 361                 /*
 362                  * Only overwrite ip-addr with allowed values
 363                  */
 364                 if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
 365                         bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte;
 366                         sprintf(str, "%ld.%ld.%ld.%ld",
 367                                 (bd->bi_ip_addr & 0xff000000) >> 24,
 368                                 (bd->bi_ip_addr & 0x00ff0000) >> 16,
 369                                 (bd->bi_ip_addr & 0x0000ff00) >> 8,
 370                                 (bd->bi_ip_addr & 0x000000ff));
 371                         setenv("ipaddr", str);
 372                 }
 373         }
 374
 375         if (cpci405_version() >= 2) {
 376                 puts("\n*** U-Boot Version does not match Board Version!\n");
 377                 puts("*** CPCI-405 Board Version 2.x detected!\n");
 378                 puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
 379         }
 380
 381 #endif /* CONFIG_CPCI405_VER2 */
 382
 383         /*
 384          * Select cts (and not dsr) on uart1
 385          */
 386         cntrl0Reg = mfdcr(cntrl0);
 387         mtdcr(cntrl0, cntrl0Reg | 0x00001000);
 388
 389         /*
 390          * Write ethernet addr in NVRAM for VxWorks
 391          */
 392         tmp = (char *)CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS;
 393         memcpy( (char *)tmp, (char *)&bd->bi_enetaddr[0], 6 );
 394         return (0);
 395 }
 396
 397
 398 /*
 399  * Check Board Identity:
 400  */
 401
 402 int checkboard (void)
 403 {
 404 #ifndef CONFIG_CPCI405_VER2
 405         int index;
 406         int len;
 407 #endif
 408         unsigned char str[64];
 409         int i = getenv_r ("serial#", str, sizeof(str));
 410         unsigned short ver;
 411
 412         puts ("Board: ");
 413
 414         if (i == -1) {
 415                 puts ("### No HW ID - assuming CPCI405");
 416         } else {
 417                 puts(str);
 418         }
 419
 420         ver = cpci405_version();
 421         printf(" (Ver %d.x, ", ver);
 422
 423 #if 0 /* test-only */
 424         if (ver >= 2) {
 425                 volatile u16 *fpga_status = (u16 *)CFG_FPGA_BASE_ADDR + 1;
 426
 427                 if (*fpga_status & CFG_FPGA_STATUS_FLASH) {
 428                         puts ("FLASH Bank B, ");
 429                 } else {
 430                         puts ("FLASH Bank A, ");
 431                 }
 432         }
 433 #endif
 434
 435         if (ctermm2()) {
 436                 printf("CTERM-M2 - Id=0x%02x)", *(unsigned char *)0xf0000400);
 437         } else {
 438                 if (cpci405_host()) {
 439                         puts ("PCI Host Version)");
 440                 } else {
 441                         puts ("PCI Adapter Version)");
 442                 }
 443         }
 444
 445 #ifndef CONFIG_CPCI405_VER2
 446         puts ("\nFPGA:  ");
 447
 448         /* display infos on fpgaimage */
 449         index = 15;
 450         for (i=0; i<4; i++) {
 451                 len = fpgadata[index];
 452                 printf("%s ", &(fpgadata[index+1]));
 453                 index += len+3;
 454         }
 455 #endif
 456
 457         putc ('\n');
 458
 459         return 0;
 460 }
 461
 462 /* ------------------------------------------------------------------------- */
 463
 464 long int initdram (int board_type)
 465 {
 466         unsigned long val;
 467
 468         mtdcr(memcfga, mem_mb0cf);
 469         val = mfdcr(memcfgd);
 470
 471 #if 0
 472         printf("\nmb0cf=%x\n", val); /* test-only */
 473         printf("strap=%x\n", mfdcr(strap)); /* test-only */
 474 #endif
 475
 476         return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 477 }
 478
 479 /* ------------------------------------------------------------------------- */
 480
 481 int testdram (void)
 482 {
 483         /* TODO: XXX XXX XXX */
 484         printf ("test: 16 MB - ok\n");
 485
 486         return (0);
 487 }
 488
 489 /* ------------------------------------------------------------------------- */
 490
 491 #ifdef CONFIG_CPCI405_VER2
 492 #ifdef CONFIG_IDE_RESET
 493
 494 void ide_set_reset(int on)
 495 {
 496         volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
 497
 498         /*
 499          * Assert or deassert CompactFlash Reset Pin
 500          */
 501         if (on) {               /* assert RESET */
 502                 *fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET);
 503         } else {                /* release RESET */
 504                 *fpga_mode |= CFG_FPGA_MODE_CF_RESET;
 505         }
 506 }
 507
 508 #endif /* CONFIG_IDE_RESET */
 509 #endif /* CONFIG_CPCI405_VER2 */
 510
 511 #if 0 /* test-only */
 512 /* ------------------------------------------------------------------------- */
 513
 514 u8 *dhcp_vendorex_prep (u8 * e)
 515 {
 516         char *ptr;
 517
 518 /* DHCP vendor-class-identifier = 60 */
 519         if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
 520                 *e++ = 60;
 521                 *e++ = strlen (ptr);
 522                 while (*ptr)
 523                         *e++ = *ptr++;
 524         }
 525 /* my DHCP_CLIENT_IDENTIFIER = 61 */
 526         if ((ptr = getenv ("dhcp_client_id"))) {
 527                 *e++ = 61;
 528                 *e++ = strlen (ptr);
 529                 while (*ptr)
 530                         *e++ = *ptr++;
 531         }
 532
 533         return e;
 534 }
 535
 536
 537 /* ------------------------------------------------------------------------- */
 538
 539 u8 *dhcp_vendorex_proc (u8 * popt)
 540 {
 541         if (*popt == 61)
 542                 return (u8 *)-1;
 543         if (*popt == 43) {
 544                 printf("|%s|", popt+4); /* test-only */
 545                 return (u8 *)-1;
 546         }
 547         return NULL;
 548 }
 549
 550 /* ------------------------------------------------------------------------- */
 551 #endif /* test-only */