board/esd/cpci405/cpci405.c

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <common.h>
   8 #include <libfdt.h>
   9 #include <fdt_support.h>
  10 #include <asm/processor.h>
  11 #include <asm/io.h>
  12 #include <command.h>
  13 #include <malloc.h>
  14 #include <net.h>
  15 #include <pci.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 extern void __ft_board_setup(void *blob, bd_t *bd);
  20
  21 #undef FPGA_DEBUG
  22
  23 /* fpga configuration data - generated by bin2cc */
  24 const unsigned char fpgadata[] =
  25 {
  26 #if defined(CONFIG_CPCI405_VER2)
  27 # if defined(CONFIG_CPCI405AB)
  28 #  include "fpgadata_cpci405ab.c"
  29 # else
  30 #  include "fpgadata_cpci4052.c"
  31 # endif
  32 #else
  33 # include "fpgadata_cpci405.c"
  34 #endif
  35 };
  36
  37 /*
  38  * include common fpga code (for esd boards)
  39  */
  40 #include "../common/fpga.c"
  41 #include "../common/auto_update.h"
  42
  43 #if defined(CONFIG_CPCI405AB)
  44 au_image_t au_image[] = {
  45         {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
  46         {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
  47         {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
  48         {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
  49         {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
  50 };
  51 #else
  52 #if defined(CONFIG_CPCI405_VER2)
  53 au_image_t au_image[] = {
  54         {"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
  55         {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
  56         {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
  57         {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
  58         {"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
  59 };
  60 #else
  61 au_image_t au_image[] = {
  62         {"cpci405/preinst.img", 0, -1, AU_SCRIPT},
  63         {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
  64         {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
  65         {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
  66         {"cpci405/postinst.img", 0, 0, AU_SCRIPT},
  67 };
  68 #endif
  69 #endif
  70
  71 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
  72
  73 /* Prototypes */
  74 int cpci405_version(void);
  75 void lxt971_no_sleep(void);
  76
  77 int board_early_init_f(void)
  78 {
  79 #ifndef CONFIG_CPCI405_VER2
  80         int index, len, i;
  81         int status;
  82 #endif
  83
  84 #ifdef FPGA_DEBUG
  85         /* set up serial port with default baudrate */
  86         (void)get_clocks();
  87         gd->baudrate = CONFIG_BAUDRATE;
  88         serial_init();
  89         console_init_f();
  90 #endif
  91
  92         /*
  93          * First pull fpga-prg pin low,
  94          * to disable fpga logic (on version 2 board)
  95          */
  96         out_be32((void *)GPIO0_ODR, 0x00000000);             /* no open drain pins      */
  97         out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output   */
  98         out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
  99         out_be32((void *)GPIO0_OR, 0);               /* pull prg low            */
 100
 101         /*
 102          * Boot onboard FPGA
 103          */
 104 #ifndef CONFIG_CPCI405_VER2
 105         if (cpci405_version() == 1) {
 106                 status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
 107                 if (status != 0) {
 108                         /* booting FPGA failed */
 109 #ifndef FPGA_DEBUG
 110                         /* set up serial port with default baudrate */
 111                         (void)get_clocks();
 112                         gd->baudrate = CONFIG_BAUDRATE;
 113                         serial_init();
 114                         console_init_f();
 115 #endif
 116                         printf("\nFPGA: Booting failed ");
 117                         switch (status) {
 118                         case ERROR_FPGA_PRG_INIT_LOW:
 119                                 printf("(Timeout: INIT not low after "
 120                                        "asserting PROGRAM*)\n ");
 121                                 break;
 122                         case ERROR_FPGA_PRG_INIT_HIGH:
 123                                 printf("(Timeout: INIT not high after "
 124                                        "deasserting PROGRAM*)\n ");
 125                                 break;
 126                         case ERROR_FPGA_PRG_DONE:
 127                                 printf("(Timeout: DONE not high after "
 128                                        "programming FPGA)\n ");
 129                                 break;
 130                         }
 131
 132                         /* display infos on fpgaimage */
 133                         index = 15;
 134                         for (i = 0; i < 4; i++) {
 135                                 len = fpgadata[index];
 136                                 printf("FPGA: %s\n", &(fpgadata[index + 1]));
 137                                 index += len + 3;
 138                         }
 139                         putc('\n');
 140                         /* delayed reboot */
 141                         for (i = 20; i > 0; i--) {
 142                                 printf("Rebooting in %2d seconds \r",i);
 143                                 for (index = 0; index < 1000; index++)
 144                                         udelay(1000);
 145                         }
 146                         putc('\n');
 147                         do_reset(NULL, 0, 0, NULL);
 148                 }
 149         }
 150 #endif /* !CONFIG_CPCI405_VER2 */
 151
 152         /*
 153          * IRQ 0-15  405GP internally generated; active high; level sensitive
 154          * IRQ 16    405GP internally generated; active low; level sensitive
 155          * IRQ 17-24 RESERVED
 156          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
 157          * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
 158          * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
 159          * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
 160          * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
 161          * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
 162          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 163          */
 164         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
 165         mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
 166         mtdcr(UIC0CR, 0x00000000);      /* set all to be non-critical*/
 167 #if defined(CONFIG_CPCI405_6U)
 168         if (cpci405_version() == 3) {
 169                 mtdcr(UIC0PR, 0xFFFFFF99);      /* set int polarities */
 170         } else {
 171                 mtdcr(UIC0PR, 0xFFFFFF81);      /* set int polarities */
 172         }
 173 #else
 174         mtdcr(UIC0PR, 0xFFFFFF81);      /* set int polarities */
 175 #endif
 176         mtdcr(UIC0TR, 0x10000000);      /* set int trigger levels */
 177         mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,
 178                                          * INT0 highest priority */
 179         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
 180
 181         return 0;
 182 }
 183
 184 int ctermm2(void)
 185 {
 186 #if defined(CONFIG_CPCI405_VER2)
 187         return 0;                       /* no, board is cpci405 */
 188 #else
 189         if ((in_8((void*)0xf0000400) == 0x00) &&
 190             (in_8((void*)0xf0000401) == 0x01))
 191                 return 0;               /* no, board is cpci405 */
 192         else
 193                 return -1;              /* yes, board is cterm-m2 */
 194 #endif
 195 }
 196
 197 int cpci405_host(void)
 198 {
 199         if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
 200                 return -1;              /* yes, board is cpci405 host */
 201         else
 202                 return 0;               /* no, board is cpci405 adapter */
 203 }
 204
 205 int cpci405_version(void)
 206 {
 207         unsigned long CPC0_CR0Reg;
 208         unsigned long value;
 209
 210         /*
 211          * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
 212          */
 213         CPC0_CR0Reg = mfdcr(CPC0_CR0);
 214         mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
 215         out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
 216         out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
 217         udelay(1000); /* wait some time before reading input */
 218         value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
 219
 220         /*
 221          * Restore GPIO settings
 222          */
 223         mtdcr(CPC0_CR0, CPC0_CR0Reg);
 224
 225         switch (value) {
 226         case 0x00180000:
 227                 /* CS2==1 && CS3==1 -> version 1 */
 228                 return 1;
 229         case 0x00080000:
 230                 /* CS2==0 && CS3==1 -> version 2 */
 231                 return 2;
 232         case 0x00100000:
 233                 /* CS2==1 && CS3==0 -> version 3 or 6U board */
 234                 return 3;
 235         case 0x00000000:
 236                 /* CS2==0 && CS3==0 -> version 4 */
 237                 return 4;
 238         default:
 239                 /* should not be reached! */
 240                 return 2;
 241         }
 242 }
 243
 244 int misc_init_r (void)
 245 {
 246         unsigned long CPC0_CR0Reg;
 247
 248         /* adjust flash start and offset */
 249         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 250         gd->bd->bi_flashoffset = 0;
 251
 252 #if defined(CONFIG_CPCI405_VER2)
 253         {
 254         unsigned char *dst;
 255         ulong len = sizeof(fpgadata);
 256         int status;
 257         int index;
 258         int i;
 259
 260         /*
 261          * On CPCI-405 version 2 the environment is saved in eeprom!
 262          * FPGA can be gzip compressed (malloc) and booted this late.
 263          */
 264         if (cpci405_version() >= 2) {
 265                 /*
 266                  * Setup GPIO pins (CS6+CS7 as GPIO)
 267                  */
 268                 CPC0_CR0Reg = mfdcr(CPC0_CR0);
 269                 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
 270
 271                 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
 272                 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
 273                            (uchar *)fpgadata, &len) != 0) {
 274                         printf("GUNZIP ERROR - must RESET board to recover\n");
 275                         do_reset(NULL, 0, 0, NULL);
 276                 }
 277
 278                 status = fpga_boot(dst, len);
 279                 if (status != 0) {
 280                         printf("\nFPGA: Booting failed ");
 281                         switch (status) {
 282                         case ERROR_FPGA_PRG_INIT_LOW:
 283                                 printf("(Timeout: INIT not low after "
 284                                        "asserting PROGRAM*)\n ");
 285                                 break;
 286                         case ERROR_FPGA_PRG_INIT_HIGH:
 287                                 printf("(Timeout: INIT not high after "
 288                                        "deasserting PROGRAM*)\n ");
 289                                 break;
 290                         case ERROR_FPGA_PRG_DONE:
 291                                 printf("(Timeout: DONE not high after "
 292                                        "programming FPGA)\n ");
 293                                 break;
 294                         }
 295
 296                         /* display infos on fpgaimage */
 297                         index = 15;
 298                         for (i = 0; i < 4; i++) {
 299                                 len = dst[index];
 300                                 printf("FPGA: %s\n", &(dst[index + 1]));
 301                                 index += len + 3;
 302                         }
 303                         putc('\n');
 304                         /* delayed reboot */
 305                         for (i = 20; i > 0; i--) {
 306                                 printf("Rebooting in %2d seconds \r", i);
 307                                 for (index = 0; index < 1000; index++)
 308                                         udelay(1000);
 309                         }
 310                         putc('\n');
 311                         do_reset(NULL, 0, 0, NULL);
 312                 }
 313
 314                 /* restore gpio/cs settings */
 315                 mtdcr(CPC0_CR0, CPC0_CR0Reg);
 316
 317                 puts("FPGA:  ");
 318
 319                 /* display infos on fpgaimage */
 320                 index = 15;
 321                 for (i = 0; i < 4; i++) {
 322                         len = dst[index];
 323                         printf("%s ", &(dst[index + 1]));
 324                         index += len + 3;
 325                 }
 326                 putc('\n');
 327
 328                 free(dst);
 329
 330                 /*
 331                  * Reset FPGA via FPGA_DATA pin
 332                  */
 333                 SET_FPGA(FPGA_PRG | FPGA_CLK);
 334                 udelay(1000); /* wait 1ms */
 335                 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 336                 udelay(1000); /* wait 1ms */
 337
 338 #if defined(CONFIG_CPCI405_6U)
 339 #error HIER GETH ES WEITER MIT IO ACCESSORS
 340                 if (cpci405_version() == 3) {
 341                         /*
 342                          * Enable outputs in fpga on version 3 board
 343                          */
 344                         out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
 345                                  in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
 346                                  CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
 347
 348                         /*
 349                          * Set outputs to 0
 350                          */
 351                         out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
 352
 353                         /*
 354                          * Reset external DUART
 355                          */
 356                         out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
 357                                  in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
 358                                  CONFIG_SYS_FPGA_MODE_DUART_RESET);
 359                         udelay(100);
 360                         out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
 361                                  in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
 362                                  ~CONFIG_SYS_FPGA_MODE_DUART_RESET);
 363                 }
 364 #endif
 365         }
 366         else {
 367                 puts("\n*** U-Boot Version does not match Board Version!\n");
 368                 puts("*** CPCI-405 Version 1.x detected!\n");
 369                 puts("*** Please use correct U-Boot version "
 370                      "(CPCI405 instead of CPCI4052)!\n\n");
 371         }
 372         }
 373 #else /* CONFIG_CPCI405_VER2 */
 374         if (cpci405_version() >= 2) {
 375                 puts("\n*** U-Boot Version does not match Board Version!\n");
 376                 puts("*** CPCI-405 Board Version 2.x detected!\n");
 377                 puts("*** Please use correct U-Boot version "
 378                      "(CPCI4052 instead of CPCI405)!\n\n");
 379         }
 380 #endif /* CONFIG_CPCI405_VER2 */
 381
 382         /*
 383          * Select cts (and not dsr) on uart1
 384          */
 385         CPC0_CR0Reg = mfdcr(CPC0_CR0);
 386         mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
 387
 388         return 0;
 389 }
 390
 391 /*
 392  * Check Board Identity:
 393  */
 394
 395 int checkboard(void)
 396 {
 397 #ifndef CONFIG_CPCI405_VER2
 398         int index;
 399         int len;
 400 #endif
 401         char str[64];
 402         int i = getenv_f("serial#", str, sizeof(str));
 403         unsigned short ver;
 404
 405         puts("Board: ");
 406
 407         if (i == -1)
 408                 puts("### No HW ID - assuming CPCI405");
 409         else
 410                 puts(str);
 411
 412         ver = cpci405_version();
 413         printf(" (Ver %d.x, ", ver);
 414
 415         if (ctermm2()) {
 416                 char str[4];
 417
 418                 /*
 419                  * Read board-id and save in env-variable
 420                  */
 421                 sprintf(str, "%d", *(unsigned char *)0xf0000400);
 422                 setenv("boardid", str);
 423                 printf("CTERM-M2 - Id=%s)", str);
 424         } else {
 425                 if (cpci405_host())
 426                         puts("PCI Host Version)");
 427                 else
 428                         puts("PCI Adapter Version)");
 429         }
 430
 431 #ifndef CONFIG_CPCI405_VER2
 432         puts("\nFPGA:   ");
 433
 434         /* display infos on fpgaimage */
 435         index = 15;
 436         for (i = 0; i < 4; i++) {
 437                 len = fpgadata[index];
 438                 printf("%s ", &(fpgadata[index + 1]));
 439                 index += len + 3;
 440         }
 441 #endif
 442
 443         putc('\n');
 444         return 0;
 445 }
 446
 447 void reset_phy(void)
 448 {
 449 #if defined(CONFIG_LXT971_NO_SLEEP)
 450
 451         /*
 452          * Disable sleep mode in LXT971
 453          */
 454         lxt971_no_sleep();
 455 #endif
 456 }
 457
 458 #if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
 459 void ide_set_reset(int on)
 460 {
 461         /*
 462          * Assert or deassert CompactFlash Reset Pin
 463          */
 464         if (on) {       /* assert RESET */
 465                 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
 466                          in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
 467                          ~CONFIG_SYS_FPGA_MODE_CF_RESET);
 468         } else {        /* release RESET */
 469                 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
 470                          in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
 471                          CONFIG_SYS_FPGA_MODE_CF_RESET);
 472         }
 473 }
 474
 475 #endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
 476
 477 #if defined(CONFIG_PCI)
 478 void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 479 {
 480         unsigned char int_line = 0xff;
 481
 482         /*
 483          * Write pci interrupt line register (cpci405 specific)
 484          */
 485         switch (PCI_DEV(dev) & 0x03) {
 486         case 0:
 487                 int_line = 27 + 2;
 488                 break;
 489         case 1:
 490                 int_line = 27 + 3;
 491                 break;
 492         case 2:
 493                 int_line = 27 + 0;
 494                 break;
 495         case 3:
 496                 int_line = 27 + 1;
 497                 break;
 498         }
 499
 500         pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
 501 }
 502
 503 int pci_pre_init(struct pci_controller *hose)
 504 {
 505         hose->fixup_irq = cpci405_pci_fixup_irq;
 506         return 1;
 507 }
 508 #endif /* defined(CONFIG_PCI) */
 509
 510 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 511 int ft_board_setup(void *blob, bd_t *bd)
 512 {
 513         int rc;
 514
 515         __ft_board_setup(blob, bd);
 516
 517         /*
 518          * Disable PCI in adapter mode.
 519          */
 520         if (!cpci405_host()) {
 521                 rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
 522                                           "disabled", sizeof("disabled"), 1);
 523                 if (rc) {
 524                         printf("Unable to update property status in PCI node, "
 525                                "err=%s\n",
 526                                fdt_strerror(rc));
 527                 }
 528         }
 529
 530         return 0;
 531 }
 532 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
 533
 534 #if defined(CONFIG_CPCI405AB)
 535 #define ONE_WIRE_CLEAR   out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +   \
 536                                           CONFIG_SYS_FPGA_MODE),        \
 537                                   in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
 538                                                   CONFIG_SYS_FPGA_MODE)) | \
 539                                           CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
 540
 541 #define ONE_WIRE_SET     out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +   \
 542                                           CONFIG_SYS_FPGA_MODE),        \
 543                                   in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
 544                                                   CONFIG_SYS_FPGA_MODE)) & \
 545                                           ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
 546
 547 #define ONE_WIRE_GET     (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
 548                                           CONFIG_SYS_FPGA_STATUS)) &  \
 549                           CONFIG_SYS_FPGA_MODE_1WIRE)
 550
 551 /*
 552  * Generate a 1-wire reset, return 1 if no presence detect was found,
 553  * return 0 otherwise.
 554  * (NOTE: Does not handle alarm presence from DS2404/DS1994)
 555  */
 556 int OWTouchReset(void)
 557 {
 558         int result;
 559
 560         ONE_WIRE_CLEAR;
 561         udelay(480);
 562         ONE_WIRE_SET;
 563         udelay(70);
 564
 565         result = ONE_WIRE_GET;
 566
 567         udelay(410);
 568         return result;
 569 }
 570
 571 /*
 572  * Send 1 a 1-wire write bit.
 573  * Provide 10us recovery time.
 574  */
 575 void OWWriteBit(int bit)
 576 {
 577         if (bit) {
 578                 /*
 579                  * write '1' bit
 580                  */
 581                 ONE_WIRE_CLEAR;
 582                 udelay(6);
 583                 ONE_WIRE_SET;
 584                 udelay(64);
 585         } else {
 586                 /*
 587                  * write '0' bit
 588                  */
 589                 ONE_WIRE_CLEAR;
 590                 udelay(60);
 591                 ONE_WIRE_SET;
 592                 udelay(10);
 593         }
 594 }
 595
 596 /*
 597  * Read a bit from the 1-wire bus and return it.
 598  * Provide 10us recovery time.
 599  */
 600 int OWReadBit(void)
 601 {
 602         int result;
 603
 604         ONE_WIRE_CLEAR;
 605         udelay(6);
 606         ONE_WIRE_SET;
 607         udelay(9);
 608
 609         result = ONE_WIRE_GET;
 610
 611         udelay(55);
 612         return result;
 613 }
 614
 615 void OWWriteByte(int data)
 616 {
 617         int loop;
 618
 619         for (loop = 0; loop < 8; loop++) {
 620                 OWWriteBit(data & 0x01);
 621                 data >>= 1;
 622         }
 623 }
 624
 625 int OWReadByte(void)
 626 {
 627         int loop, result = 0;
 628
 629         for (loop = 0; loop < 8; loop++) {
 630                 result >>= 1;
 631                 if (OWReadBit())
 632                         result |= 0x80;
 633         }
 634
 635         return result;
 636 }
 637
 638 int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 639 {
 640         unsigned short val;
 641         int result;
 642         int i;
 643         unsigned char ow_id[6];
 644         char str[32];
 645
 646         /*
 647          * Clear 1-wire bit (open drain with pull-up)
 648          */
 649         val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
 650                               CONFIG_SYS_FPGA_MODE));
 651         val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
 652         out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
 653                          CONFIG_SYS_FPGA_MODE), val);
 654
 655         result = OWTouchReset();
 656         if (result != 0)
 657                 puts("No 1-wire device detected!\n");
 658
 659         OWWriteByte(0x33); /* send read rom command */
 660         OWReadByte(); /* skip family code ( == 0x01) */
 661         for (i = 0; i < 6; i++)
 662                 ow_id[i] = OWReadByte();
 663         OWReadByte(); /* read crc */
 664
 665         sprintf(str, "%02X%02X%02X%02X%02X%02X",
 666                 ow_id[0], ow_id[1], ow_id[2], ow_id[3], ow_id[4], ow_id[5]);
 667         printf("Setting environment variable 'ow_id' to %s\n", str);
 668         setenv("ow_id", str);
 669
 670         return 0;
 671 }
 672 U_BOOT_CMD(
 673         onewire,        1,      1,      do_onewire,
 674         "Read 1-write ID",
 675         ""
 676 );
 677
 678 #define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
 679 #define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
 680
 681 /*
 682  * Write backplane ip-address...
 683  */
 684 int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 685 {
 686         char *buf;
 687         ulong crc;
 688         char str[32];
 689         char *ptr;
 690         IPaddr_t ipaddr;
 691
 692         buf = malloc(CONFIG_ENV_SIZE_2);
 693         if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
 694                         (uchar *)buf, CONFIG_ENV_SIZE_2))
 695                 puts("\nError reading backplane EEPROM!\n");
 696         else {
 697                 crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
 698                 if (crc != *(ulong *)buf) {
 699                         printf("ERROR: crc mismatch %08lx %08lx\n",
 700                                crc, *(ulong *)buf);
 701                         return -1;
 702                 }
 703
 704                 /*
 705                  * Find bp_ip
 706                  */
 707                 ptr = strstr(buf+4, "bp_ip=");
 708                 if (ptr == NULL) {
 709                         printf("ERROR: bp_ip not found!\n");
 710                         return -1;
 711                 }
 712                 ptr += 6;
 713                 ipaddr = string_to_ip(ptr);
 714
 715                 /*
 716                  * Update whole ip-addr
 717                  */
 718                 sprintf(str, "%pI4", &ipaddr);
 719                 setenv("ipaddr", str);
 720                 printf("Updated ip_addr from bp_eeprom to %s!\n", str);
 721         }
 722
 723         free(buf);
 724
 725         return 0;
 726 }
 727 U_BOOT_CMD(
 728         getbpip,        1,      1,      do_get_bpip,
 729         "Update IP-Address with Backplane IP-Address",
 730         ""
 731 );
 732
 733 /*
 734  * Set and print backplane ip...
 735  */
 736 int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 737 {
 738         char *buf;
 739         char str[32];
 740         ulong crc;
 741
 742         if (argc < 2) {
 743                 puts("ERROR!\n");
 744                 return -1;
 745         }
 746
 747         printf("Setting bp_ip to %s\n", argv[1]);
 748         buf = malloc(CONFIG_ENV_SIZE_2);
 749         memset(buf, 0, CONFIG_ENV_SIZE_2);
 750         sprintf(str, "bp_ip=%s", argv[1]);
 751         strcpy(buf+4, str);
 752         crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
 753         *(ulong *)buf = crc;
 754
 755         if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
 756                          0, (uchar *)buf, CONFIG_ENV_SIZE_2))
 757                 puts("\nError writing backplane EEPROM!\n");
 758
 759         free(buf);
 760
 761         return 0;
 762 }
 763 U_BOOT_CMD(
 764         setbpip,        2,      1,      do_set_bpip,
 765         "Write Backplane IP-Address",
 766         ""
 767 );
 768
 769 #endif /* CONFIG_CPCI405AB */