board/esd/cpci405/cpci405.c

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23 #include <common.h>
  24 #include <libfdt.h>
  25 #include <fdt_support.h>
  26 #include <asm/processor.h>
  27 #include <asm/io.h>
  28 #include <command.h>
  29 #include <malloc.h>
  30 #include <net.h>
  31 #include <pci.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
  36 extern void __ft_board_setup(void *blob, bd_t *bd);
  37
  38 #undef FPGA_DEBUG
  39
  40 /* fpga configuration data - generated by bin2cc */
  41 const unsigned char fpgadata[] =
  42 {
  43 #if defined(CONFIG_CPCI405_VER2)
  44 # if defined(CONFIG_CPCI405AB)
  45 #  include "fpgadata_cpci405ab.c"
  46 # else
  47 #  include "fpgadata_cpci4052.c"
  48 # endif
  49 #else
  50 # include "fpgadata_cpci405.c"
  51 #endif
  52 };
  53
  54 /*
  55  * include common fpga code (for esd boards)
  56  */
  57 #include "../common/fpga.c"
  58 #include "../common/auto_update.h"
  59
  60 #if defined(CONFIG_CPCI405AB)
  61 au_image_t au_image[] = {
  62         {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
  63         {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
  64         {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
  65         {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
  66         {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
  67 };
  68 #else
  69 #if defined(CONFIG_CPCI405_VER2)
  70 au_image_t au_image[] = {
  71         {"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
  72         {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
  73         {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
  74         {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
  75         {"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
  76 };
  77 #else
  78 au_image_t au_image[] = {
  79         {"cpci405/preinst.img", 0, -1, AU_SCRIPT},
  80         {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
  81         {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
  82         {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
  83         {"cpci405/postinst.img", 0, 0, AU_SCRIPT},
  84 };
  85 #endif
  86 #endif
  87
  88 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
  89
  90 /* Prototypes */
  91 int cpci405_version(void);
  92 int gunzip(void *, int, unsigned char *, unsigned long *);
  93 void lxt971_no_sleep(void);
  94
  95 int board_early_init_f(void)
  96 {
  97 #ifndef CONFIG_CPCI405_VER2
  98         int index, len, i;
  99         int status;
 100 #endif
 101
 102 #ifdef FPGA_DEBUG
 103         /* set up serial port with default baudrate */
 104         (void)get_clocks();
 105         gd->baudrate = CONFIG_BAUDRATE;
 106         serial_init();
 107         console_init_f();
 108 #endif
 109
 110         /*
 111          * First pull fpga-prg pin low,
 112          * to disable fpga logic (on version 2 board)
 113          */
 114         out_be32((void *)GPIO0_ODR, 0x00000000);             /* no open drain pins      */
 115         out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output   */
 116         out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
 117         out_be32((void *)GPIO0_OR, 0);               /* pull prg low            */
 118
 119         /*
 120          * Boot onboard FPGA
 121          */
 122 #ifndef CONFIG_CPCI405_VER2
 123         if (cpci405_version() == 1) {
 124                 status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
 125                 if (status != 0) {
 126                         /* booting FPGA failed */
 127 #ifndef FPGA_DEBUG
 128                         /* set up serial port with default baudrate */
 129                         (void)get_clocks();
 130                         gd->baudrate = CONFIG_BAUDRATE;
 131                         serial_init();
 132                         console_init_f();
 133 #endif
 134                         printf("\nFPGA: Booting failed ");
 135                         switch (status) {
 136                         case ERROR_FPGA_PRG_INIT_LOW:
 137                                 printf("(Timeout: INIT not low after "
 138                                        "asserting PROGRAM*)\n ");
 139                                 break;
 140                         case ERROR_FPGA_PRG_INIT_HIGH:
 141                                 printf("(Timeout: INIT not high after "
 142                                        "deasserting PROGRAM*)\n ");
 143                                 break;
 144                         case ERROR_FPGA_PRG_DONE:
 145                                 printf("(Timeout: DONE not high after "
 146                                        "programming FPGA)\n ");
 147                                 break;
 148                         }
 149
 150                         /* display infos on fpgaimage */
 151                         index = 15;
 152                         for (i = 0; i < 4; i++) {
 153                                 len = fpgadata[index];
 154                                 printf("FPGA: %s\n", &(fpgadata[index + 1]));
 155                                 index += len + 3;
 156                         }
 157                         putc('\n');
 158                         /* delayed reboot */
 159                         for (i = 20; i > 0; i--) {
 160                                 printf("Rebooting in %2d seconds \r",i);
 161                                 for (index = 0; index < 1000; index++)
 162                                         udelay(1000);
 163                         }
 164                         putc('\n');
 165                         do_reset(NULL, 0, 0, NULL);
 166                 }
 167         }
 168 #endif /* !CONFIG_CPCI405_VER2 */
 169
 170         /*
 171          * IRQ 0-15  405GP internally generated; active high; level sensitive
 172          * IRQ 16    405GP internally generated; active low; level sensitive
 173          * IRQ 17-24 RESERVED
 174          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
 175          * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
 176          * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
 177          * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
 178          * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
 179          * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
 180          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 181          */
 182         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 183         mtdcr(uicer, 0x00000000);       /* disable all ints */
 184         mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
 185 #if defined(CONFIG_CPCI405_6U)
 186         if (cpci405_version() == 3) {
 187                 mtdcr(uicpr, 0xFFFFFF99);       /* set int polarities */
 188         } else {
 189                 mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
 190         }
 191 #else
 192         mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
 193 #endif
 194         mtdcr(uictr, 0x10000000);       /* set int trigger levels */
 195         mtdcr(uicvcr, 0x00000001);      /* set vect base=0,
 196                                          * INT0 highest priority */
 197         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 198
 199         return 0;
 200 }
 201
 202 int ctermm2(void)
 203 {
 204 #if defined(CONFIG_CPCI405_VER2)
 205         return 0;                       /* no, board is cpci405 */
 206 #else
 207         if ((in_8((void*)0xf0000400) == 0x00) &&
 208             (in_8((void*)0xf0000401) == 0x01))
 209                 return 0;               /* no, board is cpci405 */
 210         else
 211                 return -1;              /* yes, board is cterm-m2 */
 212 #endif
 213 }
 214
 215 int cpci405_host(void)
 216 {
 217         if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
 218                 return -1;              /* yes, board is cpci405 host */
 219         else
 220                 return 0;               /* no, board is cpci405 adapter */
 221 }
 222
 223 int cpci405_version(void)
 224 {
 225         unsigned long cntrl0Reg;
 226         unsigned long value;
 227
 228         /*
 229          * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
 230          */
 231         cntrl0Reg = mfdcr(cntrl0);
 232         mtdcr(cntrl0, cntrl0Reg | 0x03000000);
 233         out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
 234         out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
 235         udelay(1000); /* wait some time before reading input */
 236         value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
 237
 238         /*
 239          * Restore GPIO settings
 240          */
 241         mtdcr(cntrl0, cntrl0Reg);
 242
 243         switch (value) {
 244         case 0x00180000:
 245                 /* CS2==1 && CS3==1 -> version 1 */
 246                 return 1;
 247         case 0x00080000:
 248                 /* CS2==0 && CS3==1 -> version 2 */
 249                 return 2;
 250         case 0x00100000:
 251                 /* CS2==1 && CS3==0 -> version 3 or 6U board */
 252                 return 3;
 253         case 0x00000000:
 254                 /* CS2==0 && CS3==0 -> version 4 */
 255                 return 4;
 256         default:
 257                 /* should not be reached! */
 258                 return 2;
 259         }
 260 }
 261
 262 int misc_init_r (void)
 263 {
 264         unsigned long cntrl0Reg;
 265
 266         /* adjust flash start and offset */
 267         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 268         gd->bd->bi_flashoffset = 0;
 269
 270 #if defined(CONFIG_CPCI405_VER2)
 271         {
 272         unsigned char *dst;
 273         ulong len = sizeof(fpgadata);
 274         int status;
 275         int index;
 276         int i;
 277
 278         /*
 279          * On CPCI-405 version 2 the environment is saved in eeprom!
 280          * FPGA can be gzip compressed (malloc) and booted this late.
 281          */
 282         if (cpci405_version() >= 2) {
 283                 /*
 284                  * Setup GPIO pins (CS6+CS7 as GPIO)
 285                  */
 286                 cntrl0Reg = mfdcr(cntrl0);
 287                 mtdcr(cntrl0, cntrl0Reg | 0x00300000);
 288
 289                 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
 290                 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
 291                            (uchar *)fpgadata, &len) != 0) {
 292                         printf("GUNZIP ERROR - must RESET board to recover\n");
 293                         do_reset(NULL, 0, 0, NULL);
 294                 }
 295
 296                 status = fpga_boot(dst, len);
 297                 if (status != 0) {
 298                         printf("\nFPGA: Booting failed ");
 299                         switch (status) {
 300                         case ERROR_FPGA_PRG_INIT_LOW:
 301                                 printf("(Timeout: INIT not low after "
 302                                        "asserting PROGRAM*)\n ");
 303                                 break;
 304                         case ERROR_FPGA_PRG_INIT_HIGH:
 305                                 printf("(Timeout: INIT not high after "
 306                                        "deasserting PROGRAM*)\n ");
 307                                 break;
 308                         case ERROR_FPGA_PRG_DONE:
 309                                 printf("(Timeout: DONE not high after "
 310                                        "programming FPGA)\n ");
 311                                 break;
 312                         }
 313
 314                         /* display infos on fpgaimage */
 315                         index = 15;
 316                         for (i = 0; i < 4; i++) {
 317                                 len = dst[index];
 318                                 printf("FPGA: %s\n", &(dst[index + 1]));
 319                                 index += len + 3;
 320                         }
 321                         putc('\n');
 322                         /* delayed reboot */
 323                         for (i = 20; i > 0; i--) {
 324                                 printf("Rebooting in %2d seconds \r", i);
 325                                 for (index = 0; index < 1000; index++)
 326                                         udelay(1000);
 327                         }
 328                         putc('\n');
 329                         do_reset(NULL, 0, 0, NULL);
 330                 }
 331
 332                 /* restore gpio/cs settings */
 333                 mtdcr(cntrl0, cntrl0Reg);
 334
 335                 puts("FPGA:  ");
 336
 337                 /* display infos on fpgaimage */
 338                 index = 15;
 339                 for (i = 0; i < 4; i++) {
 340                         len = dst[index];
 341                         printf("%s ", &(dst[index + 1]));
 342                         index += len + 3;
 343                 }
 344                 putc('\n');
 345
 346                 free(dst);
 347
 348                 /*
 349                  * Reset FPGA via FPGA_DATA pin
 350                  */
 351                 SET_FPGA(FPGA_PRG | FPGA_CLK);
 352                 udelay(1000); /* wait 1ms */
 353                 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 354                 udelay(1000); /* wait 1ms */
 355
 356 #if defined(CONFIG_CPCI405_6U)
 357 #error HIER GETH ES WEITER MIT IO ACCESSORS
 358                 if (cpci405_version() == 3) {
 359                         /*
 360                          * Enable outputs in fpga on version 3 board
 361                          */
 362                         out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
 363                                  in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
 364                                  CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
 365
 366                         /*
 367                          * Set outputs to 0
 368                          */
 369                         out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
 370
 371                         /*
 372                          * Reset external DUART
 373                          */
 374                         out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
 375                                  in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
 376                                  CONFIG_SYS_FPGA_MODE_DUART_RESET);
 377                         udelay(100);
 378                         out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
 379                                  in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
 380                                  ~CONFIG_SYS_FPGA_MODE_DUART_RESET);
 381                 }
 382 #endif
 383         }
 384         else {
 385                 puts("\n*** U-Boot Version does not match Board Version!\n");
 386                 puts("*** CPCI-405 Version 1.x detected!\n");
 387                 puts("*** Please use correct U-Boot version "
 388                      "(CPCI405 instead of CPCI4052)!\n\n");
 389         }
 390         }
 391 #else /* CONFIG_CPCI405_VER2 */
 392         if (cpci405_version() >= 2) {
 393                 puts("\n*** U-Boot Version does not match Board Version!\n");
 394                 puts("*** CPCI-405 Board Version 2.x detected!\n");
 395                 puts("*** Please use correct U-Boot version "
 396                      "(CPCI4052 instead of CPCI405)!\n\n");
 397         }
 398 #endif /* CONFIG_CPCI405_VER2 */
 399
 400         /*
 401          * Select cts (and not dsr) on uart1
 402          */
 403         cntrl0Reg = mfdcr(cntrl0);
 404         mtdcr(cntrl0, cntrl0Reg | 0x00001000);
 405
 406         return 0;
 407 }
 408
 409 /*
 410  * Check Board Identity:
 411  */
 412
 413 int checkboard(void)
 414 {
 415 #ifndef CONFIG_CPCI405_VER2
 416         int index;
 417         int len;
 418 #endif
 419         char str[64];
 420         int i = getenv_r("serial#", str, sizeof(str));
 421         unsigned short ver;
 422
 423         puts("Board: ");
 424
 425         if (i == -1)
 426                 puts("### No HW ID - assuming CPCI405");
 427         else
 428                 puts(str);
 429
 430         ver = cpci405_version();
 431         printf(" (Ver %d.x, ", ver);
 432
 433         if (ctermm2()) {
 434                 char str[4];
 435
 436                 /*
 437                  * Read board-id and save in env-variable
 438                  */
 439                 sprintf(str, "%d", *(unsigned char *)0xf0000400);
 440                 setenv("boardid", str);
 441                 printf("CTERM-M2 - Id=%s)", str);
 442         } else {
 443                 if (cpci405_host())
 444                         puts("PCI Host Version)");
 445                 else
 446                         puts("PCI Adapter Version)");
 447         }
 448
 449 #ifndef CONFIG_CPCI405_VER2
 450         puts("\nFPGA:   ");
 451
 452         /* display infos on fpgaimage */
 453         index = 15;
 454         for (i = 0; i < 4; i++) {
 455                 len = fpgadata[index];
 456                 printf("%s ", &(fpgadata[index + 1]));
 457                 index += len + 3;
 458         }
 459 #endif
 460
 461         putc('\n');
 462         return 0;
 463 }
 464
 465 void reset_phy(void)
 466 {
 467 #if defined(CONFIG_LXT971_NO_SLEEP)
 468
 469         /*
 470          * Disable sleep mode in LXT971
 471          */
 472         lxt971_no_sleep();
 473 #endif
 474 }
 475
 476 #if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
 477 void ide_set_reset(int on)
 478 {
 479         /*
 480          * Assert or deassert CompactFlash Reset Pin
 481          */
 482         if (on) {       /* assert RESET */
 483                 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
 484                          in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
 485                          ~CONFIG_SYS_FPGA_MODE_CF_RESET);
 486         } else {        /* release RESET */
 487                 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
 488                          in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
 489                          CONFIG_SYS_FPGA_MODE_CF_RESET);
 490         }
 491 }
 492
 493 #endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
 494
 495 #if defined(CONFIG_PCI)
 496 void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 497 {
 498         unsigned char int_line = 0xff;
 499
 500         /*
 501          * Write pci interrupt line register (cpci405 specific)
 502          */
 503         switch (PCI_DEV(dev) & 0x03) {
 504         case 0:
 505                 int_line = 27 + 2;
 506                 break;
 507         case 1:
 508                 int_line = 27 + 3;
 509                 break;
 510         case 2:
 511                 int_line = 27 + 0;
 512                 break;
 513         case 3:
 514                 int_line = 27 + 1;
 515                 break;
 516         }
 517
 518         pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
 519 }
 520
 521 int pci_pre_init(struct pci_controller *hose)
 522 {
 523         hose->fixup_irq = cpci405_pci_fixup_irq;
 524         return 1;
 525 }
 526 #endif /* defined(CONFIG_PCI) */
 527
 528 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 529 void ft_board_setup(void *blob, bd_t *bd)
 530 {
 531         int rc;
 532
 533         __ft_board_setup(blob, bd);
 534
 535         /*
 536          * Disable PCI in adapter mode.
 537          */
 538         if (!cpci405_host()) {
 539                 rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
 540                                           "disabled", sizeof("disabled"), 1);
 541                 if (rc) {
 542                         printf("Unable to update property status in PCI node, "
 543                                "err=%s\n",
 544                                fdt_strerror(rc));
 545                 }
 546         }
 547 }
 548 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
 549
 550 #if defined(CONFIG_CPCI405AB)
 551 #define ONE_WIRE_CLEAR   out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +   \
 552                                           CONFIG_SYS_FPGA_MODE),        \
 553                                   in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
 554                                                   CONFIG_SYS_FPGA_MODE)) | \
 555                                           CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
 556
 557 #define ONE_WIRE_SET     out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +   \
 558                                           CONFIG_SYS_FPGA_MODE),        \
 559                                   in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
 560                                                   CONFIG_SYS_FPGA_MODE)) & \
 561                                           ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
 562
 563 #define ONE_WIRE_GET     (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
 564                                           CONFIG_SYS_FPGA_STATUS)) &  \
 565                           CONFIG_SYS_FPGA_MODE_1WIRE)
 566
 567 /*
 568  * Generate a 1-wire reset, return 1 if no presence detect was found,
 569  * return 0 otherwise.
 570  * (NOTE: Does not handle alarm presence from DS2404/DS1994)
 571  */
 572 int OWTouchReset(void)
 573 {
 574         int result;
 575
 576         ONE_WIRE_CLEAR;
 577         udelay(480);
 578         ONE_WIRE_SET;
 579         udelay(70);
 580
 581         result = ONE_WIRE_GET;
 582
 583         udelay(410);
 584         return result;
 585 }
 586
 587 /*
 588  * Send 1 a 1-wire write bit.
 589  * Provide 10us recovery time.
 590  */
 591 void OWWriteBit(int bit)
 592 {
 593         if (bit) {
 594                 /*
 595                  * write '1' bit
 596                  */
 597                 ONE_WIRE_CLEAR;
 598                 udelay(6);
 599                 ONE_WIRE_SET;
 600                 udelay(64);
 601         } else {
 602                 /*
 603                  * write '0' bit
 604                  */
 605                 ONE_WIRE_CLEAR;
 606                 udelay(60);
 607                 ONE_WIRE_SET;
 608                 udelay(10);
 609         }
 610 }
 611
 612 /*
 613  * Read a bit from the 1-wire bus and return it.
 614  * Provide 10us recovery time.
 615  */
 616 int OWReadBit(void)
 617 {
 618         int result;
 619
 620         ONE_WIRE_CLEAR;
 621         udelay(6);
 622         ONE_WIRE_SET;
 623         udelay(9);
 624
 625         result = ONE_WIRE_GET;
 626
 627         udelay(55);
 628         return result;
 629 }
 630
 631 void OWWriteByte(int data)
 632 {
 633         int loop;
 634
 635         for (loop = 0; loop < 8; loop++) {
 636                 OWWriteBit(data & 0x01);
 637                 data >>= 1;
 638         }
 639 }
 640
 641 int OWReadByte(void)
 642 {
 643         int loop, result = 0;
 644
 645         for (loop = 0; loop < 8; loop++) {
 646                 result >>= 1;
 647                 if (OWReadBit())
 648                         result |= 0x80;
 649         }
 650
 651         return result;
 652 }
 653
 654 int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 655 {
 656         unsigned short val;
 657         int result;
 658         int i;
 659         unsigned char ow_id[6];
 660         char str[32];
 661         unsigned char ow_crc;
 662
 663         /*
 664          * Clear 1-wire bit (open drain with pull-up)
 665          */
 666         val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
 667                               CONFIG_SYS_FPGA_MODE));
 668         val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
 669         out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
 670                          CONFIG_SYS_FPGA_MODE), val);
 671
 672         result = OWTouchReset();
 673         if (result != 0)
 674                 puts("No 1-wire device detected!\n");
 675
 676         OWWriteByte(0x33); /* send read rom command */
 677         OWReadByte(); /* skip family code ( == 0x01) */
 678         for (i = 0; i < 6; i++)
 679                 ow_id[i] = OWReadByte();
 680         ow_crc = OWReadByte(); /* read crc */
 681
 682         sprintf(str, "%08X%04X",
 683                 *(unsigned int *)&ow_id[0],
 684                 *(unsigned short *)&ow_id[4]);
 685         printf("Setting environment variable 'ow_id' to %s\n", str);
 686         setenv("ow_id", str);
 687
 688         return 0;
 689 }
 690 U_BOOT_CMD(
 691         onewire,        1,      1,      do_onewire,
 692         "Read 1-write ID",
 693         ""
 694 );
 695
 696 #define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
 697 #define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
 698
 699 /*
 700  * Write backplane ip-address...
 701  */
 702 int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 703 {
 704         bd_t *bd = gd->bd;
 705         char *buf;
 706         ulong crc;
 707         char str[32];
 708         char *ptr;
 709         IPaddr_t ipaddr;
 710
 711         buf = malloc(CONFIG_ENV_SIZE_2);
 712         if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
 713                         (uchar *)buf, CONFIG_ENV_SIZE_2))
 714                 puts("\nError reading backplane EEPROM!\n");
 715         else {
 716                 crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
 717                 if (crc != *(ulong *)buf) {
 718                         printf("ERROR: crc mismatch %08lx %08lx\n",
 719                                crc, *(ulong *)buf);
 720                         return -1;
 721                 }
 722
 723                 /*
 724                  * Find bp_ip
 725                  */
 726                 ptr = strstr(buf+4, "bp_ip=");
 727                 if (ptr == NULL) {
 728                         printf("ERROR: bp_ip not found!\n");
 729                         return -1;
 730                 }
 731                 ptr += 6;
 732                 ipaddr = string_to_ip(ptr);
 733
 734                 /*
 735                  * Update whole ip-addr
 736                  */
 737                 bd->bi_ip_addr = ipaddr;
 738                 sprintf(str, "%ld.%ld.%ld.%ld",
 739                         (bd->bi_ip_addr & 0xff000000) >> 24,
 740                         (bd->bi_ip_addr & 0x00ff0000) >> 16,
 741                         (bd->bi_ip_addr & 0x0000ff00) >> 8,
 742                         (bd->bi_ip_addr & 0x000000ff));
 743                 setenv("ipaddr", str);
 744                 printf("Updated ip_addr from bp_eeprom to %s!\n", str);
 745         }
 746
 747         free(buf);
 748
 749         return 0;
 750 }
 751 U_BOOT_CMD(
 752         getbpip,        1,      1,      do_get_bpip,
 753         "Update IP-Address with Backplane IP-Address",
 754         ""
 755 );
 756
 757 /*
 758  * Set and print backplane ip...
 759  */
 760 int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 761 {
 762         char *buf;
 763         char str[32];
 764         ulong crc;
 765
 766         if (argc < 2) {
 767                 puts("ERROR!\n");
 768                 return -1;
 769         }
 770
 771         printf("Setting bp_ip to %s\n", argv[1]);
 772         buf = malloc(CONFIG_ENV_SIZE_2);
 773         memset(buf, 0, CONFIG_ENV_SIZE_2);
 774         sprintf(str, "bp_ip=%s", argv[1]);
 775         strcpy(buf+4, str);
 776         crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
 777         *(ulong *)buf = crc;
 778
 779         if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
 780                          0, (uchar *)buf, CONFIG_ENV_SIZE_2))
 781                 puts("\nError writing backplane EEPROM!\n");
 782
 783         free(buf);
 784
 785         return 0;
 786 }
 787 U_BOOT_CMD(
 788         setbpip,        2,      1,      do_set_bpip,
 789         "Write Backplane IP-Address",
 790         ""
 791 );
 792
 793 #endif /* CONFIG_CPCI405AB */