board/esd/cpci405/cpci405.c

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23 #include <common.h>
  24 #include <libfdt.h>
  25 #include <fdt_support.h>
  26 #include <asm/processor.h>
  27 #include <asm/io.h>
  28 #include <command.h>
  29 #include <malloc.h>
  30 #include <net.h>
  31 #include <pci.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
  36 extern void __ft_board_setup(void *blob, bd_t *bd);
  37
  38 #undef FPGA_DEBUG
  39
  40 /* fpga configuration data - generated by bin2cc */
  41 const unsigned char fpgadata[] =
  42 {
  43 #if defined(CONFIG_CPCI405_VER2)
  44 # if defined(CONFIG_CPCI405AB)
  45 #  include "fpgadata_cpci405ab.c"
  46 # else
  47 #  include "fpgadata_cpci4052.c"
  48 # endif
  49 #else
  50 # include "fpgadata_cpci405.c"
  51 #endif
  52 };
  53
  54 /*
  55  * include common fpga code (for esd boards)
  56  */
  57 #include "../common/fpga.c"
  58 #include "../common/auto_update.h"
  59
  60 #if defined(CONFIG_CPCI405AB)
  61 au_image_t au_image[] = {
  62         {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
  63         {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
  64         {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
  65         {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
  66         {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
  67 };
  68 #else
  69 #if defined(CONFIG_CPCI405_VER2)
  70 au_image_t au_image[] = {
  71         {"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
  72         {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
  73         {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
  74         {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
  75         {"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
  76 };
  77 #else
  78 au_image_t au_image[] = {
  79         {"cpci405/preinst.img", 0, -1, AU_SCRIPT},
  80         {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
  81         {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
  82         {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
  83         {"cpci405/postinst.img", 0, 0, AU_SCRIPT},
  84 };
  85 #endif
  86 #endif
  87
  88 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
  89
  90 /* Prototypes */
  91 int cpci405_version(void);
  92 void lxt971_no_sleep(void);
  93
  94 int board_early_init_f(void)
  95 {
  96 #ifndef CONFIG_CPCI405_VER2
  97         int index, len, i;
  98         int status;
  99 #endif
 100
 101 #ifdef FPGA_DEBUG
 102         /* set up serial port with default baudrate */
 103         (void)get_clocks();
 104         gd->baudrate = CONFIG_BAUDRATE;
 105         serial_init();
 106         console_init_f();
 107 #endif
 108
 109         /*
 110          * First pull fpga-prg pin low,
 111          * to disable fpga logic (on version 2 board)
 112          */
 113         out_be32((void *)GPIO0_ODR, 0x00000000);             /* no open drain pins      */
 114         out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output   */
 115         out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
 116         out_be32((void *)GPIO0_OR, 0);               /* pull prg low            */
 117
 118         /*
 119          * Boot onboard FPGA
 120          */
 121 #ifndef CONFIG_CPCI405_VER2
 122         if (cpci405_version() == 1) {
 123                 status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
 124                 if (status != 0) {
 125                         /* booting FPGA failed */
 126 #ifndef FPGA_DEBUG
 127                         /* set up serial port with default baudrate */
 128                         (void)get_clocks();
 129                         gd->baudrate = CONFIG_BAUDRATE;
 130                         serial_init();
 131                         console_init_f();
 132 #endif
 133                         printf("\nFPGA: Booting failed ");
 134                         switch (status) {
 135                         case ERROR_FPGA_PRG_INIT_LOW:
 136                                 printf("(Timeout: INIT not low after "
 137                                        "asserting PROGRAM*)\n ");
 138                                 break;
 139                         case ERROR_FPGA_PRG_INIT_HIGH:
 140                                 printf("(Timeout: INIT not high after "
 141                                        "deasserting PROGRAM*)\n ");
 142                                 break;
 143                         case ERROR_FPGA_PRG_DONE:
 144                                 printf("(Timeout: DONE not high after "
 145                                        "programming FPGA)\n ");
 146                                 break;
 147                         }
 148
 149                         /* display infos on fpgaimage */
 150                         index = 15;
 151                         for (i = 0; i < 4; i++) {
 152                                 len = fpgadata[index];
 153                                 printf("FPGA: %s\n", &(fpgadata[index + 1]));
 154                                 index += len + 3;
 155                         }
 156                         putc('\n');
 157                         /* delayed reboot */
 158                         for (i = 20; i > 0; i--) {
 159                                 printf("Rebooting in %2d seconds \r",i);
 160                                 for (index = 0; index < 1000; index++)
 161                                         udelay(1000);
 162                         }
 163                         putc('\n');
 164                         do_reset(NULL, 0, 0, NULL);
 165                 }
 166         }
 167 #endif /* !CONFIG_CPCI405_VER2 */
 168
 169         /*
 170          * IRQ 0-15  405GP internally generated; active high; level sensitive
 171          * IRQ 16    405GP internally generated; active low; level sensitive
 172          * IRQ 17-24 RESERVED
 173          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
 174          * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
 175          * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
 176          * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
 177          * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
 178          * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
 179          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 180          */
 181         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
 182         mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
 183         mtdcr(UIC0CR, 0x00000000);      /* set all to be non-critical*/
 184 #if defined(CONFIG_CPCI405_6U)
 185         if (cpci405_version() == 3) {
 186                 mtdcr(UIC0PR, 0xFFFFFF99);      /* set int polarities */
 187         } else {
 188                 mtdcr(UIC0PR, 0xFFFFFF81);      /* set int polarities */
 189         }
 190 #else
 191         mtdcr(UIC0PR, 0xFFFFFF81);      /* set int polarities */
 192 #endif
 193         mtdcr(UIC0TR, 0x10000000);      /* set int trigger levels */
 194         mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,
 195                                          * INT0 highest priority */
 196         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
 197
 198         return 0;
 199 }
 200
 201 int ctermm2(void)
 202 {
 203 #if defined(CONFIG_CPCI405_VER2)
 204         return 0;                       /* no, board is cpci405 */
 205 #else
 206         if ((in_8((void*)0xf0000400) == 0x00) &&
 207             (in_8((void*)0xf0000401) == 0x01))
 208                 return 0;               /* no, board is cpci405 */
 209         else
 210                 return -1;              /* yes, board is cterm-m2 */
 211 #endif
 212 }
 213
 214 int cpci405_host(void)
 215 {
 216         if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
 217                 return -1;              /* yes, board is cpci405 host */
 218         else
 219                 return 0;               /* no, board is cpci405 adapter */
 220 }
 221
 222 int cpci405_version(void)
 223 {
 224         unsigned long CPC0_CR0Reg;
 225         unsigned long value;
 226
 227         /*
 228          * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
 229          */
 230         CPC0_CR0Reg = mfdcr(CPC0_CR0);
 231         mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
 232         out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
 233         out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
 234         udelay(1000); /* wait some time before reading input */
 235         value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
 236
 237         /*
 238          * Restore GPIO settings
 239          */
 240         mtdcr(CPC0_CR0, CPC0_CR0Reg);
 241
 242         switch (value) {
 243         case 0x00180000:
 244                 /* CS2==1 && CS3==1 -> version 1 */
 245                 return 1;
 246         case 0x00080000:
 247                 /* CS2==0 && CS3==1 -> version 2 */
 248                 return 2;
 249         case 0x00100000:
 250                 /* CS2==1 && CS3==0 -> version 3 or 6U board */
 251                 return 3;
 252         case 0x00000000:
 253                 /* CS2==0 && CS3==0 -> version 4 */
 254                 return 4;
 255         default:
 256                 /* should not be reached! */
 257                 return 2;
 258         }
 259 }
 260
 261 int misc_init_r (void)
 262 {
 263         unsigned long CPC0_CR0Reg;
 264
 265         /* adjust flash start and offset */
 266         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 267         gd->bd->bi_flashoffset = 0;
 268
 269 #if defined(CONFIG_CPCI405_VER2)
 270         {
 271         unsigned char *dst;
 272         ulong len = sizeof(fpgadata);
 273         int status;
 274         int index;
 275         int i;
 276
 277         /*
 278          * On CPCI-405 version 2 the environment is saved in eeprom!
 279          * FPGA can be gzip compressed (malloc) and booted this late.
 280          */
 281         if (cpci405_version() >= 2) {
 282                 /*
 283                  * Setup GPIO pins (CS6+CS7 as GPIO)
 284                  */
 285                 CPC0_CR0Reg = mfdcr(CPC0_CR0);
 286                 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
 287
 288                 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
 289                 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
 290                            (uchar *)fpgadata, &len) != 0) {
 291                         printf("GUNZIP ERROR - must RESET board to recover\n");
 292                         do_reset(NULL, 0, 0, NULL);
 293                 }
 294
 295                 status = fpga_boot(dst, len);
 296                 if (status != 0) {
 297                         printf("\nFPGA: Booting failed ");
 298                         switch (status) {
 299                         case ERROR_FPGA_PRG_INIT_LOW:
 300                                 printf("(Timeout: INIT not low after "
 301                                        "asserting PROGRAM*)\n ");
 302                                 break;
 303                         case ERROR_FPGA_PRG_INIT_HIGH:
 304                                 printf("(Timeout: INIT not high after "
 305                                        "deasserting PROGRAM*)\n ");
 306                                 break;
 307                         case ERROR_FPGA_PRG_DONE:
 308                                 printf("(Timeout: DONE not high after "
 309                                        "programming FPGA)\n ");
 310                                 break;
 311                         }
 312
 313                         /* display infos on fpgaimage */
 314                         index = 15;
 315                         for (i = 0; i < 4; i++) {
 316                                 len = dst[index];
 317                                 printf("FPGA: %s\n", &(dst[index + 1]));
 318                                 index += len + 3;
 319                         }
 320                         putc('\n');
 321                         /* delayed reboot */
 322                         for (i = 20; i > 0; i--) {
 323                                 printf("Rebooting in %2d seconds \r", i);
 324                                 for (index = 0; index < 1000; index++)
 325                                         udelay(1000);
 326                         }
 327                         putc('\n');
 328                         do_reset(NULL, 0, 0, NULL);
 329                 }
 330
 331                 /* restore gpio/cs settings */
 332                 mtdcr(CPC0_CR0, CPC0_CR0Reg);
 333
 334                 puts("FPGA:  ");
 335
 336                 /* display infos on fpgaimage */
 337                 index = 15;
 338                 for (i = 0; i < 4; i++) {
 339                         len = dst[index];
 340                         printf("%s ", &(dst[index + 1]));
 341                         index += len + 3;
 342                 }
 343                 putc('\n');
 344
 345                 free(dst);
 346
 347                 /*
 348                  * Reset FPGA via FPGA_DATA pin
 349                  */
 350                 SET_FPGA(FPGA_PRG | FPGA_CLK);
 351                 udelay(1000); /* wait 1ms */
 352                 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 353                 udelay(1000); /* wait 1ms */
 354
 355 #if defined(CONFIG_CPCI405_6U)
 356 #error HIER GETH ES WEITER MIT IO ACCESSORS
 357                 if (cpci405_version() == 3) {
 358                         /*
 359                          * Enable outputs in fpga on version 3 board
 360                          */
 361                         out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
 362                                  in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
 363                                  CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
 364
 365                         /*
 366                          * Set outputs to 0
 367                          */
 368                         out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
 369
 370                         /*
 371                          * Reset external DUART
 372                          */
 373                         out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
 374                                  in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
 375                                  CONFIG_SYS_FPGA_MODE_DUART_RESET);
 376                         udelay(100);
 377                         out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
 378                                  in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
 379                                  ~CONFIG_SYS_FPGA_MODE_DUART_RESET);
 380                 }
 381 #endif
 382         }
 383         else {
 384                 puts("\n*** U-Boot Version does not match Board Version!\n");
 385                 puts("*** CPCI-405 Version 1.x detected!\n");
 386                 puts("*** Please use correct U-Boot version "
 387                      "(CPCI405 instead of CPCI4052)!\n\n");
 388         }
 389         }
 390 #else /* CONFIG_CPCI405_VER2 */
 391         if (cpci405_version() >= 2) {
 392                 puts("\n*** U-Boot Version does not match Board Version!\n");
 393                 puts("*** CPCI-405 Board Version 2.x detected!\n");
 394                 puts("*** Please use correct U-Boot version "
 395                      "(CPCI4052 instead of CPCI405)!\n\n");
 396         }
 397 #endif /* CONFIG_CPCI405_VER2 */
 398
 399         /*
 400          * Select cts (and not dsr) on uart1
 401          */
 402         CPC0_CR0Reg = mfdcr(CPC0_CR0);
 403         mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
 404
 405         return 0;
 406 }
 407
 408 /*
 409  * Check Board Identity:
 410  */
 411
 412 int checkboard(void)
 413 {
 414 #ifndef CONFIG_CPCI405_VER2
 415         int index;
 416         int len;
 417 #endif
 418         char str[64];
 419         int i = getenv_f("serial#", str, sizeof(str));
 420         unsigned short ver;
 421
 422         puts("Board: ");
 423
 424         if (i == -1)
 425                 puts("### No HW ID - assuming CPCI405");
 426         else
 427                 puts(str);
 428
 429         ver = cpci405_version();
 430         printf(" (Ver %d.x, ", ver);
 431
 432         if (ctermm2()) {
 433                 char str[4];
 434
 435                 /*
 436                  * Read board-id and save in env-variable
 437                  */
 438                 sprintf(str, "%d", *(unsigned char *)0xf0000400);
 439                 setenv("boardid", str);
 440                 printf("CTERM-M2 - Id=%s)", str);
 441         } else {
 442                 if (cpci405_host())
 443                         puts("PCI Host Version)");
 444                 else
 445                         puts("PCI Adapter Version)");
 446         }
 447
 448 #ifndef CONFIG_CPCI405_VER2
 449         puts("\nFPGA:   ");
 450
 451         /* display infos on fpgaimage */
 452         index = 15;
 453         for (i = 0; i < 4; i++) {
 454                 len = fpgadata[index];
 455                 printf("%s ", &(fpgadata[index + 1]));
 456                 index += len + 3;
 457         }
 458 #endif
 459
 460         putc('\n');
 461         return 0;
 462 }
 463
 464 void reset_phy(void)
 465 {
 466 #if defined(CONFIG_LXT971_NO_SLEEP)
 467
 468         /*
 469          * Disable sleep mode in LXT971
 470          */
 471         lxt971_no_sleep();
 472 #endif
 473 }
 474
 475 #if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
 476 void ide_set_reset(int on)
 477 {
 478         /*
 479          * Assert or deassert CompactFlash Reset Pin
 480          */
 481         if (on) {       /* assert RESET */
 482                 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
 483                          in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
 484                          ~CONFIG_SYS_FPGA_MODE_CF_RESET);
 485         } else {        /* release RESET */
 486                 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
 487                          in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
 488                          CONFIG_SYS_FPGA_MODE_CF_RESET);
 489         }
 490 }
 491
 492 #endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
 493
 494 #if defined(CONFIG_PCI)
 495 void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 496 {
 497         unsigned char int_line = 0xff;
 498
 499         /*
 500          * Write pci interrupt line register (cpci405 specific)
 501          */
 502         switch (PCI_DEV(dev) & 0x03) {
 503         case 0:
 504                 int_line = 27 + 2;
 505                 break;
 506         case 1:
 507                 int_line = 27 + 3;
 508                 break;
 509         case 2:
 510                 int_line = 27 + 0;
 511                 break;
 512         case 3:
 513                 int_line = 27 + 1;
 514                 break;
 515         }
 516
 517         pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
 518 }
 519
 520 int pci_pre_init(struct pci_controller *hose)
 521 {
 522         hose->fixup_irq = cpci405_pci_fixup_irq;
 523         return 1;
 524 }
 525 #endif /* defined(CONFIG_PCI) */
 526
 527 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 528 void ft_board_setup(void *blob, bd_t *bd)
 529 {
 530         int rc;
 531
 532         __ft_board_setup(blob, bd);
 533
 534         /*
 535          * Disable PCI in adapter mode.
 536          */
 537         if (!cpci405_host()) {
 538                 rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
 539                                           "disabled", sizeof("disabled"), 1);
 540                 if (rc) {
 541                         printf("Unable to update property status in PCI node, "
 542                                "err=%s\n",
 543                                fdt_strerror(rc));
 544                 }
 545         }
 546 }
 547 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
 548
 549 #if defined(CONFIG_CPCI405AB)
 550 #define ONE_WIRE_CLEAR   out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +   \
 551                                           CONFIG_SYS_FPGA_MODE),        \
 552                                   in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
 553                                                   CONFIG_SYS_FPGA_MODE)) | \
 554                                           CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
 555
 556 #define ONE_WIRE_SET     out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +   \
 557                                           CONFIG_SYS_FPGA_MODE),        \
 558                                   in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
 559                                                   CONFIG_SYS_FPGA_MODE)) & \
 560                                           ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
 561
 562 #define ONE_WIRE_GET     (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
 563                                           CONFIG_SYS_FPGA_STATUS)) &  \
 564                           CONFIG_SYS_FPGA_MODE_1WIRE)
 565
 566 /*
 567  * Generate a 1-wire reset, return 1 if no presence detect was found,
 568  * return 0 otherwise.
 569  * (NOTE: Does not handle alarm presence from DS2404/DS1994)
 570  */
 571 int OWTouchReset(void)
 572 {
 573         int result;
 574
 575         ONE_WIRE_CLEAR;
 576         udelay(480);
 577         ONE_WIRE_SET;
 578         udelay(70);
 579
 580         result = ONE_WIRE_GET;
 581
 582         udelay(410);
 583         return result;
 584 }
 585
 586 /*
 587  * Send 1 a 1-wire write bit.
 588  * Provide 10us recovery time.
 589  */
 590 void OWWriteBit(int bit)
 591 {
 592         if (bit) {
 593                 /*
 594                  * write '1' bit
 595                  */
 596                 ONE_WIRE_CLEAR;
 597                 udelay(6);
 598                 ONE_WIRE_SET;
 599                 udelay(64);
 600         } else {
 601                 /*
 602                  * write '0' bit
 603                  */
 604                 ONE_WIRE_CLEAR;
 605                 udelay(60);
 606                 ONE_WIRE_SET;
 607                 udelay(10);
 608         }
 609 }
 610
 611 /*
 612  * Read a bit from the 1-wire bus and return it.
 613  * Provide 10us recovery time.
 614  */
 615 int OWReadBit(void)
 616 {
 617         int result;
 618
 619         ONE_WIRE_CLEAR;
 620         udelay(6);
 621         ONE_WIRE_SET;
 622         udelay(9);
 623
 624         result = ONE_WIRE_GET;
 625
 626         udelay(55);
 627         return result;
 628 }
 629
 630 void OWWriteByte(int data)
 631 {
 632         int loop;
 633
 634         for (loop = 0; loop < 8; loop++) {
 635                 OWWriteBit(data & 0x01);
 636                 data >>= 1;
 637         }
 638 }
 639
 640 int OWReadByte(void)
 641 {
 642         int loop, result = 0;
 643
 644         for (loop = 0; loop < 8; loop++) {
 645                 result >>= 1;
 646                 if (OWReadBit())
 647                         result |= 0x80;
 648         }
 649
 650         return result;
 651 }
 652
 653 int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 654 {
 655         unsigned short val;
 656         int result;
 657         int i;
 658         unsigned char ow_id[6];
 659         char str[32];
 660         unsigned char ow_crc;
 661
 662         /*
 663          * Clear 1-wire bit (open drain with pull-up)
 664          */
 665         val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
 666                               CONFIG_SYS_FPGA_MODE));
 667         val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
 668         out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
 669                          CONFIG_SYS_FPGA_MODE), val);
 670
 671         result = OWTouchReset();
 672         if (result != 0)
 673                 puts("No 1-wire device detected!\n");
 674
 675         OWWriteByte(0x33); /* send read rom command */
 676         OWReadByte(); /* skip family code ( == 0x01) */
 677         for (i = 0; i < 6; i++)
 678                 ow_id[i] = OWReadByte();
 679         ow_crc = OWReadByte(); /* read crc */
 680
 681         sprintf(str, "%08X%04X",
 682                 *(unsigned int *)&ow_id[0],
 683                 *(unsigned short *)&ow_id[4]);
 684         printf("Setting environment variable 'ow_id' to %s\n", str);
 685         setenv("ow_id", str);
 686
 687         return 0;
 688 }
 689 U_BOOT_CMD(
 690         onewire,        1,      1,      do_onewire,
 691         "Read 1-write ID",
 692         ""
 693 );
 694
 695 #define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
 696 #define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
 697
 698 /*
 699  * Write backplane ip-address...
 700  */
 701 int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 702 {
 703         bd_t *bd = gd->bd;
 704         char *buf;
 705         ulong crc;
 706         char str[32];
 707         char *ptr;
 708         IPaddr_t ipaddr;
 709
 710         buf = malloc(CONFIG_ENV_SIZE_2);
 711         if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
 712                         (uchar *)buf, CONFIG_ENV_SIZE_2))
 713                 puts("\nError reading backplane EEPROM!\n");
 714         else {
 715                 crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
 716                 if (crc != *(ulong *)buf) {
 717                         printf("ERROR: crc mismatch %08lx %08lx\n",
 718                                crc, *(ulong *)buf);
 719                         return -1;
 720                 }
 721
 722                 /*
 723                  * Find bp_ip
 724                  */
 725                 ptr = strstr(buf+4, "bp_ip=");
 726                 if (ptr == NULL) {
 727                         printf("ERROR: bp_ip not found!\n");
 728                         return -1;
 729                 }
 730                 ptr += 6;
 731                 ipaddr = string_to_ip(ptr);
 732
 733                 /*
 734                  * Update whole ip-addr
 735                  */
 736                 bd->bi_ip_addr = ipaddr;
 737                 sprintf(str, "%ld.%ld.%ld.%ld",
 738                         (bd->bi_ip_addr & 0xff000000) >> 24,
 739                         (bd->bi_ip_addr & 0x00ff0000) >> 16,
 740                         (bd->bi_ip_addr & 0x0000ff00) >> 8,
 741                         (bd->bi_ip_addr & 0x000000ff));
 742                 setenv("ipaddr", str);
 743                 printf("Updated ip_addr from bp_eeprom to %s!\n", str);
 744         }
 745
 746         free(buf);
 747
 748         return 0;
 749 }
 750 U_BOOT_CMD(
 751         getbpip,        1,      1,      do_get_bpip,
 752         "Update IP-Address with Backplane IP-Address",
 753         ""
 754 );
 755
 756 /*
 757  * Set and print backplane ip...
 758  */
 759 int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 760 {
 761         char *buf;
 762         char str[32];
 763         ulong crc;
 764
 765         if (argc < 2) {
 766                 puts("ERROR!\n");
 767                 return -1;
 768         }
 769
 770         printf("Setting bp_ip to %s\n", argv[1]);
 771         buf = malloc(CONFIG_ENV_SIZE_2);
 772         memset(buf, 0, CONFIG_ENV_SIZE_2);
 773         sprintf(str, "bp_ip=%s", argv[1]);
 774         strcpy(buf+4, str);
 775         crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
 776         *(ulong *)buf = crc;
 777
 778         if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
 779                          0, (uchar *)buf, CONFIG_ENV_SIZE_2))
 780                 puts("\nError writing backplane EEPROM!\n");
 781
 782         free(buf);
 783
 784         return 0;
 785 }
 786 U_BOOT_CMD(
 787         setbpip,        2,      1,      do_set_bpip,
 788         "Write Backplane IP-Address",
 789         ""
 790 );
 791
 792 #endif /* CONFIG_CPCI405AB */