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[people/ms/u-boot.git] / board / esd / cpci750 / cpci750.c
1 /*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
24 * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
25 */
26
27 /*
28 * cpci750.c - main board support/init for the esd cpci750.
29 */
30
31 #include <common.h>
32 #include <command.h>
33 #include <74xx_7xx.h>
34 #include "../../Marvell/include/memory.h"
35 #include "../../Marvell/include/pci.h"
36 #include "../../Marvell/include/mv_gen_reg.h"
37 #include <net.h>
38
39 #include "eth.h"
40 #include "mpsc.h"
41 #include "i2c.h"
42 #include "64360.h"
43 #include "mv_regs.h"
44
45 #undef DEBUG
46 /*#define DEBUG */
47
48 #ifdef CONFIG_PCI
49 #define MAP_PCI
50 #endif /* of CONFIG_PCI */
51
52 #ifdef DEBUG
53 #define DP(x) x
54 #else
55 #define DP(x)
56 #endif
57
58 extern void flush_data_cache (void);
59 extern void invalidate_l1_instruction_cache (void);
60 extern flash_info_t flash_info[];
61
62 /* ------------------------------------------------------------------------- */
63
64 /* this is the current GT register space location */
65 /* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
66
67 /* Unfortunately, we cant change it while we are in flash, so we initialize it
68 * to the "final" value. This means that any debug_led calls before
69 * board_early_init_f wont work right (like in cpu_init_f).
70 * See also my_remap_gt_regs below. (NTL)
71 */
72
73 void board_prebootm_init (void);
74 unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
75 int display_mem_map (void);
76
77 /* ------------------------------------------------------------------------- */
78
79 /*
80 * This is a version of the GT register space remapping function that
81 * doesn't touch globals (meaning, it's ok to run from flash.)
82 *
83 * Unfortunately, this has the side effect that a writable
84 * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
85 */
86
87 void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
88 {
89 u32 temp;
90
91 /* check and see if it's already moved */
92
93 /* original ppcboot 1.1.6 source
94
95 temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
96 if ((temp & 0xffff) == new_loc >> 20)
97 return;
98
99 temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
100 0xffff0000) | (new_loc >> 20);
101
102 out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
103
104 while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
105 original ppcboot 1.1.6 source end */
106
107 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
108 if ((temp & 0xffff) == new_loc >> 16)
109 return;
110
111 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
112 0xffff0000) | (new_loc >> 16);
113
114 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
115
116 while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
117 }
118
119 #ifdef CONFIG_PCI
120
121 static void gt_pci_config (void)
122 {
123 unsigned int stat;
124 unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
125
126 /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
127 * config registers by writing ones to the bus and device.
128 * We then update the Virtual register with the correct value for the bus and device.
129 */
130 if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
131 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
132
133 GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
134
135 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
136 GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
137 (stat & 0xffff0000) | CFG_PCI_IDSEL);
138
139 }
140 if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
141 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
142 GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
143
144 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
145 GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
146 (stat & 0xffff0000) | CFG_PCI_IDSEL);
147 }
148
149 /* Enable master */
150 PCI_MASTER_ENABLE (0, SELF);
151 PCI_MASTER_ENABLE (1, SELF);
152
153 /* Enable PCI0/1 Mem0 and IO 0 disable all others */
154 GT_REG_READ (BASE_ADDR_ENABLE, &stat);
155 stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
156 <<
157 18);
158 stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
159 GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
160
161 /* ronen- add write to pci remap registers for 64460.
162 in 64360 when writing to pci base go and overide remap automaticaly,
163 in 64460 it doesn't */
164 GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16);
165 GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16);
166 GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
167
168 GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
169 GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
170 GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
171
172 GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16);
173 GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16);
174 GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
175
176 GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
177 GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
178 GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
179
180 /* PCI interface settings */
181 /* Timeout set to retry forever */
182 GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
183 GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
184
185 /* ronen - enable only CS0 and Internal reg!! */
186 GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
187 GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
188
189 /*ronen update the pci internal registers base address.*/
190 #ifdef MAP_PCI
191 for (stat = 0; stat <= PCI_HOST1; stat++)
192 pciWriteConfigReg (stat,
193 PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
194 SELF, CFG_GT_REGS);
195 #endif
196
197 }
198 #endif
199
200 /* Setup CPU interface paramaters */
201 static void gt_cpu_config (void)
202 {
203 cpu_t cpu = get_cpu_type ();
204 ulong tmp;
205
206 /* cpu configuration register */
207 tmp = GTREGREAD (CPU_CONFIGURATION);
208
209 /* set the SINGLE_CPU bit see MV64360 P.399 */
210 #ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
211 tmp |= CPU_CONF_SINGLE_CPU;
212 #endif
213
214 tmp &= ~CPU_CONF_AACK_DELAY_2;
215
216 tmp |= CPU_CONF_DP_VALID;
217 tmp |= CPU_CONF_AP_VALID;
218
219 tmp |= CPU_CONF_PIPELINE;
220
221 GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
222
223 /* CPU master control register */
224 tmp = GTREGREAD (CPU_MASTER_CONTROL);
225
226 tmp |= CPU_MAST_CTL_ARB_EN;
227
228 if ((cpu == CPU_7400) ||
229 (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
230
231 tmp |= CPU_MAST_CTL_CLEAN_BLK;
232 tmp |= CPU_MAST_CTL_FLUSH_BLK;
233
234 } else {
235 /* cleanblock must be cleared for CPUs
236 * that do not support this command (603e, 750)
237 * see Res#1 */
238 tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
239 tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
240 }
241 GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
242 }
243
244 /*
245 * board_early_init_f.
246 *
247 * set up gal. device mappings, etc.
248 */
249 int board_early_init_f (void)
250 {
251
252 /*
253 * set up the GT the way the kernel wants it
254 * the call to move the GT register space will obviously
255 * fail if it has already been done, but we're going to assume
256 * that if it's not at the power-on location, it's where we put
257 * it last time. (huber)
258 */
259
260 my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
261
262 /* No PCI in first release of Port To_do: enable it. */
263 #ifdef CONFIG_PCI
264 gt_pci_config ();
265 #endif
266 /* mask all external interrupt sources */
267 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
268 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
269 /* new in MV6436x */
270 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
271 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
272 /* --------------------- */
273 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
274 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
275 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
276 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
277 /* does not exist in MV6436x
278 GT_REG_WRITE(CPU_INT_0_MASK, 0);
279 GT_REG_WRITE(CPU_INT_1_MASK, 0);
280 GT_REG_WRITE(CPU_INT_2_MASK, 0);
281 GT_REG_WRITE(CPU_INT_3_MASK, 0);
282 --------------------- */
283
284
285 /* ----- DEVICE BUS SETTINGS ------ */
286
287 /*
288 * EVB
289 * 0 - SRAM ????
290 * 1 - RTC ????
291 * 2 - UART ????
292 * 3 - Flash checked 32Bit Intel Strata
293 * boot - BootCS checked 8Bit 29LV040B
294 *
295 */
296
297 /*
298 * the dual 7450 module requires burst access to the boot
299 * device, so the serial rom copies the boot device to the
300 * on-board sram on the eval board, and updates the correct
301 * registers to boot from the sram. (device0)
302 */
303
304 memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
305 memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
306 memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
307 memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
308
309
310 /* configure device timing */
311 GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
312 GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
313 GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
314 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_DEV3_PAR);
315
316 #ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
317 /* detect if we are booting from the 32 bit flash */
318 if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
319 /* 32 bit boot flash */
320 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
321 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
322 CFG_32BIT_BOOT_PAR);
323 } else {
324 /* 8 bit boot flash */
325 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
326 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
327 }
328 #else
329 /* 8 bit boot flash only */
330 /* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
331 #endif
332
333
334 gt_cpu_config ();
335
336 /* MPP setup */
337 GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
338 GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
339 GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
340 GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
341
342 GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
343 DEBUG_LED0_ON ();
344 DEBUG_LED1_ON ();
345 DEBUG_LED2_ON ();
346
347 return 0;
348 }
349
350 /* various things to do after relocation */
351
352 int misc_init_r ()
353 {
354 icache_enable ();
355 #ifdef CFG_L2
356 l2cache_enable ();
357 #endif
358 #ifdef CONFIG_MPSC
359
360 mpsc_sdma_init ();
361 mpsc_init2 ();
362 #endif
363
364 #if 0
365 /* disable the dcache and MMU */
366 dcache_lock ();
367 #endif
368 if (flash_info[3].size < CFG_FLASH_INCREMENT) {
369 unsigned int flash_offset;
370 unsigned int l;
371
372 flash_offset = CFG_FLASH_INCREMENT - flash_info[3].size;
373 for (l = 0; l < CFG_MAX_FLASH_SECT; l++) {
374 if (flash_info[3].start[l] != 0) {
375 flash_info[3].start[l] += flash_offset;
376 }
377 }
378 flash_protect (FLAG_PROTECT_SET,
379 CFG_MONITOR_BASE,
380 CFG_MONITOR_BASE + monitor_flash_len - 1,
381 &flash_info[3]);
382 }
383 return 0;
384 }
385
386 void after_reloc (ulong dest_addr, gd_t * gd)
387 {
388
389 memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE);
390
391 display_mem_map ();
392 /* now, jump to the main ppcboot board init code */
393 board_init_r (gd, dest_addr);
394 /* NOTREACHED */
395 }
396
397 /* ------------------------------------------------------------------------- */
398
399 /*
400 * Check Board Identity:
401 *
402 * right now, assume borad type. (there is just one...after all)
403 */
404
405 int checkboard (void)
406 {
407 int l_type = 0;
408
409 printf ("BOARD: %s\n", CFG_BOARD_NAME);
410 return (l_type);
411 }
412
413 /* utility functions */
414 void debug_led (int led, int mode)
415 {
416 }
417
418 int display_mem_map (void)
419 {
420 int i, j;
421 unsigned int base, size, width;
422
423 /* SDRAM */
424 printf ("SD (DDR) RAM\n");
425 for (i = 0; i <= BANK3; i++) {
426 base = memoryGetBankBaseAddress (i);
427 size = memoryGetBankSize (i);
428 if (size != 0) {
429 printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
430 i, base, size >> 20);
431 }
432 }
433 #ifdef CONFIG_PCI
434 /* CPU's PCI windows */
435 for (i = 0; i <= PCI_HOST1; i++) {
436 printf ("\nCPU's PCI %d windows\n", i);
437 base = pciGetSpaceBase (i, PCI_IO);
438 size = pciGetSpaceSize (i, PCI_IO);
439 printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
440 size >> 20);
441 for (j = 0;
442 j <=
443 PCI_REGION0
444 /*ronen currently only first PCI MEM is used 3 */ ;
445 j++) {
446 base = pciGetSpaceBase (i, j);
447 size = pciGetSpaceSize (i, j);
448 printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
449 }
450 }
451 #endif /* of CONFIG_PCI */
452 /* Devices */
453 printf ("\nDEVICES\n");
454 for (i = 0; i <= DEVICE3; i++) {
455 base = memoryGetDeviceBaseAddress (i);
456 size = memoryGetDeviceSize (i);
457 width = memoryGetDeviceWidth (i) * 8;
458 printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
459 if (i == 0)
460 printf ("\t- FLASH\n");
461 else if (i == 1)
462 printf ("\t- FLASH\n");
463 else if (i == 2)
464 printf ("\t- FLASH\n");
465 else
466 printf ("\t- RTC/REGS/CAN\n");
467 }
468
469 /* Bootrom */
470 base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
471 size = memoryGetDeviceSize (BOOT_DEVICE);
472 width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
473 printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n",
474 base, size >> 20, width);
475 return (0);
476 }
477
478 /* DRAM check routines copied from gw8260 */
479
480 #if defined (CFG_DRAM_TEST)
481
482 /*********************************************************************/
483 /* NAME: move64() - moves a double word (64-bit) */
484 /* */
485 /* DESCRIPTION: */
486 /* this function performs a double word move from the data at */
487 /* the source pointer to the location at the destination pointer. */
488 /* */
489 /* INPUTS: */
490 /* unsigned long long *src - pointer to data to move */
491 /* */
492 /* OUTPUTS: */
493 /* unsigned long long *dest - pointer to locate to move data */
494 /* */
495 /* RETURNS: */
496 /* None */
497 /* */
498 /* RESTRICTIONS/LIMITATIONS: */
499 /* May cloober fr0. */
500 /* */
501 /*********************************************************************/
502 static void move64 (unsigned long long *src, unsigned long long *dest)
503 {
504 asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
505 "stfd 0, 0(4)" /* *dest = fpr0 */
506 : : : "fr0"); /* Clobbers fr0 */
507 return;
508 }
509
510
511 #if defined (CFG_DRAM_TEST_DATA)
512
513 unsigned long long pattern[] = {
514 0xaaaaaaaaaaaaaaaaLL,
515 0xccccccccccccccccLL,
516 0xf0f0f0f0f0f0f0f0LL,
517 0xff00ff00ff00ff00LL,
518 0xffff0000ffff0000LL,
519 0xffffffff00000000LL,
520 0x00000000ffffffffLL,
521 0x0000ffff0000ffffLL,
522 0x00ff00ff00ff00ffLL,
523 0x0f0f0f0f0f0f0f0fLL,
524 0x3333333333333333LL,
525 0x5555555555555555LL,
526 };
527
528 /*********************************************************************/
529 /* NAME: mem_test_data() - test data lines for shorts and opens */
530 /* */
531 /* DESCRIPTION: */
532 /* Tests data lines for shorts and opens by forcing adjacent data */
533 /* to opposite states. Because the data lines could be routed in */
534 /* an arbitrary manner the must ensure test patterns ensure that */
535 /* every case is tested. By using the following series of binary */
536 /* patterns every combination of adjacent bits is test regardless */
537 /* of routing. */
538 /* */
539 /* ...101010101010101010101010 */
540 /* ...110011001100110011001100 */
541 /* ...111100001111000011110000 */
542 /* ...111111110000000011111111 */
543 /* */
544 /* Carrying this out, gives us six hex patterns as follows: */
545 /* */
546 /* 0xaaaaaaaaaaaaaaaa */
547 /* 0xcccccccccccccccc */
548 /* 0xf0f0f0f0f0f0f0f0 */
549 /* 0xff00ff00ff00ff00 */
550 /* 0xffff0000ffff0000 */
551 /* 0xffffffff00000000 */
552 /* */
553 /* The number test patterns will always be given by: */
554 /* */
555 /* log(base 2)(number data bits) = log2 (64) = 6 */
556 /* */
557 /* To test for short and opens to other signals on our boards. we */
558 /* simply */
559 /* test with the 1's complemnt of the paterns as well. */
560 /* */
561 /* OUTPUTS: */
562 /* Displays failing test pattern */
563 /* */
564 /* RETURNS: */
565 /* 0 - Passed test */
566 /* 1 - Failed test */
567 /* */
568 /* RESTRICTIONS/LIMITATIONS: */
569 /* Assumes only one one SDRAM bank */
570 /* */
571 /*********************************************************************/
572 int mem_test_data (void)
573 {
574 unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
575 unsigned long long temp64 = 0;
576 int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
577 int i;
578 unsigned int hi, lo;
579
580 for (i = 0; i < num_patterns; i++) {
581 move64 (&(pattern[i]), pmem);
582 move64 (pmem, &temp64);
583
584 /* hi = (temp64>>32) & 0xffffffff; */
585 /* lo = temp64 & 0xffffffff; */
586 /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
587
588 hi = (pattern[i] >> 32) & 0xffffffff;
589 lo = pattern[i] & 0xffffffff;
590 /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
591
592 if (temp64 != pattern[i]) {
593 printf ("\n Data Test Failed, pattern 0x%08x%08x",
594 hi, lo);
595 return 1;
596 }
597 }
598
599 return 0;
600 }
601 #endif /* CFG_DRAM_TEST_DATA */
602
603 #if defined (CFG_DRAM_TEST_ADDRESS)
604 /*********************************************************************/
605 /* NAME: mem_test_address() - test address lines */
606 /* */
607 /* DESCRIPTION: */
608 /* This function performs a test to verify that each word im */
609 /* memory is uniquly addressable. The test sequence is as follows: */
610 /* */
611 /* 1) write the address of each word to each word. */
612 /* 2) verify that each location equals its address */
613 /* */
614 /* OUTPUTS: */
615 /* Displays failing test pattern and address */
616 /* */
617 /* RETURNS: */
618 /* 0 - Passed test */
619 /* 1 - Failed test */
620 /* */
621 /* RESTRICTIONS/LIMITATIONS: */
622 /* */
623 /* */
624 /*********************************************************************/
625 int mem_test_address (void)
626 {
627 volatile unsigned int *pmem =
628 (volatile unsigned int *) CFG_MEMTEST_START;
629 const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
630 unsigned int i;
631
632 /* write address to each location */
633 for (i = 0; i < size; i++) {
634 pmem[i] = i;
635 }
636
637 /* verify each loaction */
638 for (i = 0; i < size; i++) {
639 if (pmem[i] != i) {
640 printf ("\n Address Test Failed at 0x%x", i);
641 return 1;
642 }
643 }
644 return 0;
645 }
646 #endif /* CFG_DRAM_TEST_ADDRESS */
647
648 #if defined (CFG_DRAM_TEST_WALK)
649 /*********************************************************************/
650 /* NAME: mem_march() - memory march */
651 /* */
652 /* DESCRIPTION: */
653 /* Marches up through memory. At each location verifies rmask if */
654 /* read = 1. At each location write wmask if write = 1. Displays */
655 /* failing address and pattern. */
656 /* */
657 /* INPUTS: */
658 /* volatile unsigned long long * base - start address of test */
659 /* unsigned int size - number of dwords(64-bit) to test */
660 /* unsigned long long rmask - read verify mask */
661 /* unsigned long long wmask - wrtie verify mask */
662 /* short read - verifies rmask if read = 1 */
663 /* short write - writes wmask if write = 1 */
664 /* */
665 /* OUTPUTS: */
666 /* Displays failing test pattern and address */
667 /* */
668 /* RETURNS: */
669 /* 0 - Passed test */
670 /* 1 - Failed test */
671 /* */
672 /* RESTRICTIONS/LIMITATIONS: */
673 /* */
674 /* */
675 /*********************************************************************/
676 int mem_march (volatile unsigned long long *base,
677 unsigned int size,
678 unsigned long long rmask,
679 unsigned long long wmask, short read, short write)
680 {
681 unsigned int i;
682 unsigned long long temp = 0;
683 unsigned int hitemp, lotemp, himask, lomask;
684
685 for (i = 0; i < size; i++) {
686 if (read != 0) {
687 /* temp = base[i]; */
688 move64 ((unsigned long long *) &(base[i]), &temp);
689 if (rmask != temp) {
690 hitemp = (temp >> 32) & 0xffffffff;
691 lotemp = temp & 0xffffffff;
692 himask = (rmask >> 32) & 0xffffffff;
693 lomask = rmask & 0xffffffff;
694
695 printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
696 return 1;
697 }
698 }
699 if (write != 0) {
700 /* base[i] = wmask; */
701 move64 (&wmask, (unsigned long long *) &(base[i]));
702 }
703 }
704 return 0;
705 }
706 #endif /* CFG_DRAM_TEST_WALK */
707
708 /*********************************************************************/
709 /* NAME: mem_test_walk() - a simple walking ones test */
710 /* */
711 /* DESCRIPTION: */
712 /* Performs a walking ones through entire physical memory. The */
713 /* test uses as series of memory marches, mem_march(), to verify */
714 /* and write the test patterns to memory. The test sequence is as */
715 /* follows: */
716 /* 1) march writing 0000...0001 */
717 /* 2) march verifying 0000...0001 , writing 0000...0010 */
718 /* 3) repeat step 2 shifting masks left 1 bit each time unitl */
719 /* the write mask equals 1000...0000 */
720 /* 4) march verifying 1000...0000 */
721 /* The test fails if any of the memory marches return a failure. */
722 /* */
723 /* OUTPUTS: */
724 /* Displays which pass on the memory test is executing */
725 /* */
726 /* RETURNS: */
727 /* 0 - Passed test */
728 /* 1 - Failed test */
729 /* */
730 /* RESTRICTIONS/LIMITATIONS: */
731 /* */
732 /* */
733 /*********************************************************************/
734 int mem_test_walk (void)
735 {
736 unsigned long long mask;
737 volatile unsigned long long *pmem =
738 (volatile unsigned long long *) CFG_MEMTEST_START;
739 const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
740
741 unsigned int i;
742
743 mask = 0x01;
744
745 printf ("Initial Pass");
746 mem_march (pmem, size, 0x0, 0x1, 0, 1);
747
748 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
749 printf (" ");
750 printf (" ");
751 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
752
753 for (i = 0; i < 63; i++) {
754 printf ("Pass %2d", i + 2);
755 if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
756 /*printf("mask: 0x%x, pass: %d, ", mask, i); */
757 return 1;
758 }
759 mask = mask << 1;
760 printf ("\b\b\b\b\b\b\b");
761 }
762
763 printf ("Last Pass");
764 if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
765 /* printf("mask: 0x%x", mask); */
766 return 1;
767 }
768 printf ("\b\b\b\b\b\b\b\b\b");
769 printf (" ");
770 printf ("\b\b\b\b\b\b\b\b\b");
771
772 return 0;
773 }
774
775 /*********************************************************************/
776 /* NAME: testdram() - calls any enabled memory tests */
777 /* */
778 /* DESCRIPTION: */
779 /* Runs memory tests if the environment test variables are set to */
780 /* 'y'. */
781 /* */
782 /* INPUTS: */
783 /* testdramdata - If set to 'y', data test is run. */
784 /* testdramaddress - If set to 'y', address test is run. */
785 /* testdramwalk - If set to 'y', walking ones test is run */
786 /* */
787 /* OUTPUTS: */
788 /* None */
789 /* */
790 /* RETURNS: */
791 /* 0 - Passed test */
792 /* 1 - Failed test */
793 /* */
794 /* RESTRICTIONS/LIMITATIONS: */
795 /* */
796 /* */
797 /*********************************************************************/
798 int testdram (void)
799 {
800 char *s;
801 int rundata = 0;
802 int runaddress = 0;
803 int runwalk = 0;
804
805 #ifdef CFG_DRAM_TEST_DATA
806 s = getenv ("testdramdata");
807 rundata = (s && (*s == 'y')) ? 1 : 0;
808 #endif
809 #ifdef CFG_DRAM_TEST_ADDRESS
810 s = getenv ("testdramaddress");
811 runaddress = (s && (*s == 'y')) ? 1 : 0;
812 #endif
813 #ifdef CFG_DRAM_TEST_WALK
814 s = getenv ("testdramwalk");
815 runwalk = (s && (*s == 'y')) ? 1 : 0;
816 #endif
817
818 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
819 printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
820 }
821 #ifdef CFG_DRAM_TEST_DATA
822 if (rundata == 1) {
823 printf ("Test DATA ... ");
824 if (mem_test_data () == 1) {
825 printf ("failed \n");
826 return 1;
827 } else
828 printf ("ok \n");
829 }
830 #endif
831 #ifdef CFG_DRAM_TEST_ADDRESS
832 if (runaddress == 1) {
833 printf ("Test ADDRESS ... ");
834 if (mem_test_address () == 1) {
835 printf ("failed \n");
836 return 1;
837 } else
838 printf ("ok \n");
839 }
840 #endif
841 #ifdef CFG_DRAM_TEST_WALK
842 if (runwalk == 1) {
843 printf ("Test WALKING ONEs ... ");
844 if (mem_test_walk () == 1) {
845 printf ("failed \n");
846 return 1;
847 } else
848 printf ("ok \n");
849 }
850 #endif
851 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
852 printf ("passed\n");
853 }
854 return 0;
855
856 }
857 #endif /* CFG_DRAM_TEST */
858
859 /* ronen - the below functions are used by the bootm function */
860 /* - we map the base register to fbe00000 (same mapping as in the LSP) */
861 /* - we turn off the RX gig dmas - to prevent the dma from overunning */
862 /* the kernel data areas. */
863 /* - we diable and invalidate the icache and dcache. */
864 void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
865 {
866 u32 temp;
867
868 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
869 if ((temp & 0xffff) == new_loc >> 16)
870 return;
871
872 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
873 0xffff0000) | (new_loc >> 16);
874
875 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
876
877 while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
878 new_loc |
879 (INTERNAL_SPACE_DECODE)))))
880 != temp);
881
882 }
883
884 void board_prebootm_init ()
885 {
886
887 /* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
888 GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
889
890 /* Stop GigE Rx DMA engines */
891 GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
892 /* GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); */
893 /* GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */
894
895 /* Relocate MV64360 internal regs */
896 my_remap_gt_regs_bootm (CFG_GT_REGS, CFG_DFL_GT_REGS);
897
898 icache_disable ();
899 invalidate_l1_instruction_cache ();
900 flush_data_cache ();
901 dcache_disable ();
902 }
903
904
905 int do_show_cfg(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
906 {
907 unsigned int reset_sample_low;
908 unsigned int reset_sample_high;
909
910 GT_REG_READ(0x3c4, &reset_sample_low);
911 GT_REG_READ(0x3d4, &reset_sample_high);
912 printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
913
914 return(0);
915 }
916
917 U_BOOT_CMD(
918 show_cfg, 1, 1, do_show_cfg,
919 "show_cfg- Show Marvell strapping register\n",
920 "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n"
921 );
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