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[people/ms/u-boot.git] / board / esd / cpci750 / mpsc.c
1 /*
2 * (C) Copyright 2001
3 * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*************************************************************************
25 * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
26 *
27 ************************************************************************/
28
29 /*
30 * mpsc.c - driver for console over the MPSC.
31 */
32
33
34 #include <common.h>
35 #include <config.h>
36 #include <asm/cache.h>
37
38 #include <malloc.h>
39 #include "mpsc.h"
40
41 #include "mv_regs.h"
42
43 #include "../../Marvell/include/memory.h"
44
45 /* Define this if you wish to use the MPSC as a register based UART.
46 * This will force the serial port to not use the SDMA engine at all.
47 */
48
49 #undef CONFIG_MPSC_DEBUG_PORT
50
51
52 int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
53 char (*mpsc_getchar) (void) = mpsc_getchar_debug;
54 int (*mpsc_test_char) (void) = mpsc_test_char_debug;
55
56
57 static volatile unsigned int *rx_desc_base = NULL;
58 static unsigned int rx_desc_index = 0;
59 static volatile unsigned int *tx_desc_base = NULL;
60 static unsigned int tx_desc_index = 0;
61
62 /* local function declarations */
63 static int galmpsc_connect (int channel, int connect);
64 static int galmpsc_route_rx_clock (int channel, int brg);
65 static int galmpsc_route_tx_clock (int channel, int brg);
66 static int galmpsc_write_config_regs (int mpsc, int mode);
67 static int galmpsc_config_channel_regs (int mpsc);
68 static int galmpsc_set_char_length (int mpsc, int value);
69 static int galmpsc_set_stop_bit_length (int mpsc, int value);
70 static int galmpsc_set_parity (int mpsc, int value);
71 static int galmpsc_enter_hunt (int mpsc);
72 static int galmpsc_set_brkcnt (int mpsc, int value);
73 static int galmpsc_set_tcschar (int mpsc, int value);
74 static int galmpsc_set_snoop (int mpsc, int value);
75 static int galmpsc_shutdown (int mpsc);
76
77 static int galsdma_set_RFT (int channel);
78 static int galsdma_set_SFM (int channel);
79 static int galsdma_set_rxle (int channel);
80 static int galsdma_set_txle (int channel);
81 static int galsdma_set_burstsize (int channel, unsigned int value);
82 static int galsdma_set_RC (int channel, unsigned int value);
83
84 static int galbrg_set_CDV (int channel, int value);
85 static int galbrg_enable (int channel);
86 static int galbrg_disable (int channel);
87 static int galbrg_set_clksrc (int channel, int value);
88 static int galbrg_set_CUV (int channel, int value);
89
90 static void galsdma_enable_rx (void);
91 static int galsdma_set_mem_space (unsigned int memSpace,
92 unsigned int memSpaceTarget,
93 unsigned int memSpaceAttr,
94 unsigned int baseAddress,
95 unsigned int size);
96
97
98 #define SOFTWARE_CACHE_MANAGEMENT
99
100 #ifdef SOFTWARE_CACHE_MANAGEMENT
101 #define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
102 #define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
103 #define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
104 #else
105 #define FLUSH_DCACHE(a,b)
106 #define FLUSH_AND_INVALIDATE_DCACHE(a,b)
107 #define INVALIDATE_DCACHE(a,b)
108 #endif
109
110 #ifdef CONFIG_MPSC_DEBUG_PORT
111 static void mpsc_debug_init (void)
112 {
113
114 volatile unsigned int temp;
115
116 /* Clear the CFR (CHR4) */
117 /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
118 temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
119 temp &= 0xffffff00;
120 temp |= BIT29;
121 GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
122 temp);
123
124 /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
125 temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
126 temp |= (BIT12 | BIT15);
127 GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
128 temp);
129
130 /* Set int mask */
131 temp = GTREGREAD (GALMPSC_0_INT_MASK);
132 temp |= BIT6;
133 GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
134 }
135 #endif
136
137 char mpsc_getchar_debug (void)
138 {
139 volatile int temp;
140 volatile unsigned int cause;
141
142 cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
143 while ((cause & BIT6) == 0) {
144 cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
145 }
146
147 temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
148 (CHANNEL * GALMPSC_REG_GAP));
149 /* By writing 1's to the set bits, the register is cleared */
150 GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
151 temp);
152 GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
153 return (temp >> 16) & 0xff;
154 }
155
156 /* special function for running out of flash. doesn't modify any
157 * global variables [josh] */
158 int mpsc_putchar_early (char ch)
159 {
160 DECLARE_GLOBAL_DATA_PTR;
161 int mpsc = CHANNEL;
162 int temp =
163 GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
164 galmpsc_set_tcschar (mpsc, ch);
165 GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
166 temp | 0x200);
167
168 #define MAGIC_FACTOR (10*1000000)
169
170 udelay (MAGIC_FACTOR / gd->baudrate);
171 return 0;
172 }
173
174 /* This is used after relocation, see serial.c and mpsc_init2 */
175 static int mpsc_putchar_sdma (char ch)
176 {
177 volatile unsigned int *p;
178 unsigned int temp;
179
180
181 /* align the descriptor */
182 p = tx_desc_base;
183 memset ((void *) p, 0, 8 * sizeof (unsigned int));
184
185 /* fill one 64 bit buffer */
186 /* word swap, pad with 0 */
187 p[4] = 0; /* x */
188 p[5] = (unsigned int) ch; /* x */
189
190 /* CHANGED completely according to GT64260A dox - NTL */
191 p[0] = 0x00010001; /* 0 */
192 p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */
193 p[2] = 0; /* 8 */
194 p[3] = (unsigned int) &p[4]; /* c */
195
196 #if 0
197 p[9] = DESC_FIRST | DESC_LAST;
198 p[10] = (unsigned int) &p[0];
199 p[11] = (unsigned int) &p[12];
200 #endif
201
202 FLUSH_DCACHE (&p[0], &p[8]);
203
204 GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
205 (unsigned int) &p[0]);
206 GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
207 (unsigned int) &p[0]);
208
209 temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
210 temp |= (TX_DEMAND | TX_STOP);
211 GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
212
213 INVALIDATE_DCACHE (&p[1], &p[2]);
214
215 while (p[1] & DESC_OWNER_BIT) {
216 udelay (100);
217 INVALIDATE_DCACHE (&p[1], &p[2]);
218 }
219 return 0;
220 }
221
222 char mpsc_getchar_sdma (void)
223 {
224 static unsigned int done = 0;
225 volatile char ch;
226 unsigned int len = 0, idx = 0, temp;
227
228 volatile unsigned int *p;
229
230
231 do {
232 p = &rx_desc_base[rx_desc_index * 8];
233
234 INVALIDATE_DCACHE (&p[0], &p[1]);
235 /* Wait for character */
236 while (p[1] & DESC_OWNER_BIT) {
237 udelay (100);
238 INVALIDATE_DCACHE (&p[0], &p[1]);
239 }
240
241 /* Handle error case */
242 if (p[1] & (1 << 15)) {
243 printf ("oops, error: %08x\n", p[1]);
244
245 temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
246 (CHANNEL * GALMPSC_REG_GAP));
247 temp |= (1 << 23);
248 GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
249 (CHANNEL * GALMPSC_REG_GAP), temp);
250
251 /* Can't poll on abort bit, so we just wait. */
252 udelay (100);
253
254 galsdma_enable_rx ();
255 }
256
257 /* Number of bytes left in this descriptor */
258 len = p[0] & 0xffff;
259
260 if (len) {
261 /* Where to look */
262 idx = 5;
263 if (done > 3)
264 idx = 4;
265 if (done > 7)
266 idx = 7;
267 if (done > 11)
268 idx = 6;
269
270 INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
271 ch = p[idx] & 0xff;
272 done++;
273 }
274
275 if (done < len) {
276 /* this descriptor has more bytes still
277 * shift down the char we just read, and leave the
278 * buffer in place for the next time around
279 */
280 p[idx] = p[idx] >> 8;
281 FLUSH_DCACHE (&p[idx], &p[idx + 1]);
282 }
283
284 if (done == len) {
285 /* nothing left in this descriptor.
286 * go to next one
287 */
288 p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
289 p[0] = 0x00100000;
290 FLUSH_DCACHE (&p[0], &p[1]);
291 /* Next descriptor */
292 rx_desc_index = (rx_desc_index + 1) % RX_DESC;
293 done = 0;
294 }
295 } while (len == 0); /* galileo bug.. len might be zero */
296
297 return ch;
298 }
299
300
301 int mpsc_test_char_debug (void)
302 {
303 if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
304 return 0;
305 else {
306 return 1;
307 }
308 }
309
310
311 int mpsc_test_char_sdma (void)
312 {
313 volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
314
315 INVALIDATE_DCACHE (&p[1], &p[2]);
316
317 if (p[1] & DESC_OWNER_BIT)
318 return 0;
319 else
320 return 1;
321 }
322
323 int mpsc_init (int baud)
324 {
325 /* BRG CONFIG */
326 galbrg_set_baudrate (CHANNEL, baud);
327 galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */
328 galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */
329 galbrg_enable (CHANNEL); /* Enable BRG */
330
331 /* Set up clock routing */
332 galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */
333
334 galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */
335 galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */
336
337 /* reset MPSC state */
338 galmpsc_shutdown (CHANNEL);
339
340 /* SDMA CONFIG */
341 galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */
342 galsdma_set_txle (CHANNEL);
343 galsdma_set_rxle (CHANNEL);
344 galsdma_set_RC (CHANNEL, 0xf);
345 galsdma_set_SFM (CHANNEL);
346 galsdma_set_RFT (CHANNEL);
347
348 /* MPSC CONFIG */
349 galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
350 galmpsc_config_channel_regs (CHANNEL);
351 galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */
352 galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */
353 galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */
354
355 #ifdef CONFIG_MPSC_DEBUG_PORT
356 mpsc_debug_init ();
357 #endif
358
359 /* COMM_MPSC CONFIG */
360 #ifdef SOFTWARE_CACHE_MANAGEMENT
361 galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */
362 #else
363 galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */
364 #endif
365
366 return 0;
367 }
368
369
370 void mpsc_sdma_init (void)
371 {
372 /* Setup SDMA channel0 SDMA_CONFIG_REG*/
373 GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
374
375 /* Enable MPSC-Window0 for DRAM Bank0 */
376 if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT,
377 MV64360_SDMA_DRAM_CS_0_TARGET,
378 0,
379 memoryGetBankBaseAddress
380 (CS_0_LOW_DECODE_ADDRESS),
381 memoryGetBankSize (BANK0)) != true)
382 printf ("%s: SDMA_Window0 memory setup failed !!! \n",
383 __FUNCTION__);
384
385
386 /* Disable MPSC-Window1 */
387 if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT,
388 MV64360_SDMA_DRAM_CS_0_TARGET,
389 0,
390 memoryGetBankBaseAddress
391 (CS_1_LOW_DECODE_ADDRESS),
392 memoryGetBankSize (BANK3)) != true)
393 printf ("%s: SDMA_Window1 memory setup failed !!! \n",
394 __FUNCTION__);
395
396
397 /* Disable MPSC-Window2 */
398 if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT,
399 MV64360_SDMA_DRAM_CS_0_TARGET,
400 0,
401 memoryGetBankBaseAddress
402 (CS_2_LOW_DECODE_ADDRESS),
403 memoryGetBankSize (BANK3)) != true)
404 printf ("%s: SDMA_Window2 memory setup failed !!! \n",
405 __FUNCTION__);
406
407
408 /* Disable MPSC-Window3 */
409 if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT,
410 MV64360_SDMA_DRAM_CS_0_TARGET,
411 0,
412 memoryGetBankBaseAddress
413 (CS_3_LOW_DECODE_ADDRESS),
414 memoryGetBankSize (BANK3)) != true)
415 printf ("%s: SDMA_Window3 memory setup failed !!! \n",
416 __FUNCTION__);
417
418 /* Setup MPSC0 access mode Window0 full access */
419 GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
420 (MV64360_SDMA_WIN_ACCESS_FULL <<
421 (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
422
423 /* Setup MPSC1 access mode Window1 full access */
424 GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
425 (MV64360_SDMA_WIN_ACCESS_FULL <<
426 (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
427
428 /* Setup MPSC internal address space base address */
429 GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
430
431 /* no high address remap*/
432 GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
433 GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
434
435 /* clear interrupt cause register for MPSC (fault register)*/
436 GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
437 }
438
439
440 void mpsc_init2 (void)
441 {
442 int i;
443
444 #ifndef CONFIG_MPSC_DEBUG_PORT
445 mpsc_putchar = mpsc_putchar_sdma;
446 mpsc_getchar = mpsc_getchar_sdma;
447 mpsc_test_char = mpsc_test_char_sdma;
448 #endif
449 /* RX descriptors */
450 rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
451 sizeof (unsigned int));
452
453 /* align descriptors */
454 rx_desc_base = (unsigned int *)
455 (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
456
457 rx_desc_index = 0;
458
459 memset ((void *) rx_desc_base, 0,
460 (RX_DESC * 8) * sizeof (unsigned int));
461
462 for (i = 0; i < RX_DESC; i++) {
463 rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */
464 rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */
465 rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */
466 rx_desc_base[i * 8] = 0x00100000;
467 }
468 rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
469
470 FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
471 GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
472 (unsigned int) &rx_desc_base[0]);
473
474 /* TX descriptors */
475 tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
476 sizeof (unsigned int));
477
478 /* align descriptors */
479 tx_desc_base = (unsigned int *)
480 (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
481
482 tx_desc_index = -1;
483
484 memset ((void *) tx_desc_base, 0,
485 (TX_DESC * 8) * sizeof (unsigned int));
486
487 for (i = 0; i < TX_DESC; i++) {
488 tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
489 tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
490 tx_desc_base[i * 8 + 3] =
491 (unsigned int) &tx_desc_base[i * 8 + 4];
492 tx_desc_base[i * 8 + 2] =
493 (unsigned int) &tx_desc_base[(i + 1) * 8];
494 tx_desc_base[i * 8 + 1] =
495 DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
496
497 /* set sbytecnt and shadow byte cnt to 1 */
498 tx_desc_base[i * 8] = 0x00010001;
499 }
500 tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
501
502 FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
503
504 udelay (100);
505
506 galsdma_enable_rx ();
507
508 return;
509 }
510
511 int galbrg_set_baudrate (int channel, int rate)
512 {
513 DECLARE_GLOBAL_DATA_PTR;
514 int clock;
515
516 galbrg_disable (channel); /*ok */
517
518 #ifdef ZUMA_NTL
519 /* from tclk */
520 clock = (CFG_TCLK / (16 * rate)) - 1;
521 #else
522 clock = (CFG_TCLK / (16 * rate)) - 1;
523 #endif
524
525 galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */
526
527 galbrg_enable (channel);
528
529 gd->baudrate = rate;
530
531 return 0;
532 }
533
534 /* ------------------------------------------------------------------ */
535
536 /* Below are all the private functions that no one else needs */
537
538 static int galbrg_set_CDV (int channel, int value)
539 {
540 unsigned int temp;
541
542 temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
543 temp &= 0xFFFF0000;
544 temp |= (value & 0x0000FFFF);
545 GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
546
547 return 0;
548 }
549
550 static int galbrg_enable (int channel)
551 {
552 unsigned int temp;
553
554 temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
555 temp |= 0x00010000;
556 GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
557
558 return 0;
559 }
560
561 static int galbrg_disable (int channel)
562 {
563 unsigned int temp;
564
565 temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
566 temp &= 0xFFFEFFFF;
567 GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
568
569 return 0;
570 }
571
572 static int galbrg_set_clksrc (int channel, int value)
573 {
574 unsigned int temp;
575
576 temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
577 temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */
578 temp |= (value << 18);
579 GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
580 return 0;
581 }
582
583 static int galbrg_set_CUV (int channel, int value)
584 {
585 /* set CountUpValue */
586 GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
587
588 return 0;
589 }
590
591 #if 0
592 static int galbrg_reset (int channel)
593 {
594 unsigned int temp;
595
596 temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
597 temp |= 0x20000;
598 GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
599
600 return 0;
601 }
602 #endif
603
604 static int galsdma_set_RFT (int channel)
605 {
606 unsigned int temp;
607
608 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
609 temp |= 0x00000001;
610 GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
611 temp);
612
613 return 0;
614 }
615
616 static int galsdma_set_SFM (int channel)
617 {
618 unsigned int temp;
619
620 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
621 temp |= 0x00000002;
622 GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
623 temp);
624
625 return 0;
626 }
627
628 static int galsdma_set_rxle (int channel)
629 {
630 unsigned int temp;
631
632 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
633 temp |= 0x00000040;
634 GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
635 temp);
636
637 return 0;
638 }
639
640 static int galsdma_set_txle (int channel)
641 {
642 unsigned int temp;
643
644 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
645 temp |= 0x00000080;
646 GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
647 temp);
648
649 return 0;
650 }
651
652 static int galsdma_set_RC (int channel, unsigned int value)
653 {
654 unsigned int temp;
655
656 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
657 temp &= ~0x0000003c;
658 temp |= (value << 2);
659 GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
660 temp);
661
662 return 0;
663 }
664
665 static int galsdma_set_burstsize (int channel, unsigned int value)
666 {
667 unsigned int temp;
668
669 temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
670 temp &= 0xFFFFCFFF;
671 switch (value) {
672 case 8:
673 GT_REG_WRITE (GALSDMA_0_CONF_REG +
674 (channel * GALSDMA_REG_DIFF),
675 (temp | (0x3 << 12)));
676 break;
677
678 case 4:
679 GT_REG_WRITE (GALSDMA_0_CONF_REG +
680 (channel * GALSDMA_REG_DIFF),
681 (temp | (0x2 << 12)));
682 break;
683
684 case 2:
685 GT_REG_WRITE (GALSDMA_0_CONF_REG +
686 (channel * GALSDMA_REG_DIFF),
687 (temp | (0x1 << 12)));
688 break;
689
690 case 1:
691 GT_REG_WRITE (GALSDMA_0_CONF_REG +
692 (channel * GALSDMA_REG_DIFF),
693 (temp | (0x0 << 12)));
694 break;
695
696 default:
697 return -1;
698 break;
699 }
700
701 return 0;
702 }
703
704 static int galmpsc_connect (int channel, int connect)
705 {
706 unsigned int temp;
707
708 temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
709
710 if ((channel == 0) && connect)
711 temp &= ~0x00000007;
712 else if ((channel == 1) && connect)
713 temp &= ~(0x00000007 << 6);
714 else if ((channel == 0) && !connect)
715 temp |= 0x00000007;
716 else
717 temp |= (0x00000007 << 6);
718
719 /* Just in case... */
720 temp &= 0x3fffffff;
721
722 GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
723
724 return 0;
725 }
726
727 static int galmpsc_route_rx_clock (int channel, int brg)
728 {
729 unsigned int temp;
730
731 temp = GTREGREAD (GALMPSC_RxC_ROUTE);
732
733 if (channel == 0) {
734 temp &= ~0x0000000F;
735 temp |= brg;
736 } else {
737 temp &= ~0x00000F00;
738 temp |= (brg << 8);
739 }
740
741 GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
742
743 return 0;
744 }
745
746 static int galmpsc_route_tx_clock (int channel, int brg)
747 {
748 unsigned int temp;
749
750 temp = GTREGREAD (GALMPSC_TxC_ROUTE);
751
752 if (channel == 0) {
753 temp &= ~0x0000000F;
754 temp |= brg;
755 } else {
756 temp &= ~0x00000F00;
757 temp |= (brg << 8);
758 }
759
760 GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
761
762 return 0;
763 }
764
765 static int galmpsc_write_config_regs (int mpsc, int mode)
766 {
767 if (mode == GALMPSC_UART) {
768 /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
769 GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
770 0x000004c4);
771
772 /* Main config reg High (32x Rx/Tx clock mode, width=8bits */
773 GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
774 0x024003f8);
775 /* 22 2222 1111 */
776 /* 54 3210 9876 */
777 /* 0000 0010 0000 0000 */
778 /* 1 */
779 /* 098 7654 3210 */
780 /* 0000 0011 1111 1000 */
781 } else
782 return -1;
783
784 return 0;
785 }
786
787 static int galmpsc_config_channel_regs (int mpsc)
788 {
789 GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
790 GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
791 GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
792 GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
793 GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
794 GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
795 GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
796 GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
797 GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
798 GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
799
800 galmpsc_set_brkcnt (mpsc, 0x3);
801 galmpsc_set_tcschar (mpsc, 0xab);
802
803 return 0;
804 }
805
806 static int galmpsc_set_brkcnt (int mpsc, int value)
807 {
808 unsigned int temp;
809
810 temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
811 temp &= 0x0000FFFF;
812 temp |= (value << 16);
813 GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
814
815 return 0;
816 }
817
818 static int galmpsc_set_tcschar (int mpsc, int value)
819 {
820 unsigned int temp;
821
822 temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
823 temp &= 0xFFFF0000;
824 temp |= value;
825 GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
826
827 return 0;
828 }
829
830 static int galmpsc_set_char_length (int mpsc, int value)
831 {
832 unsigned int temp;
833
834 temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
835 temp &= 0xFFFFCFFF;
836 temp |= (value << 12);
837 GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
838
839 return 0;
840 }
841
842 static int galmpsc_set_stop_bit_length (int mpsc, int value)
843 {
844 unsigned int temp;
845
846 temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
847 temp &= 0xFFFFBFFF;
848 temp |= (value << 14);
849 GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
850
851 return 0;
852 }
853
854 static int galmpsc_set_parity (int mpsc, int value)
855 {
856 unsigned int temp;
857
858 temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
859 if (value != -1) {
860 temp &= 0xFFF3FFF3;
861 temp |= ((value << 18) | (value << 2));
862 temp |= ((value << 17) | (value << 1));
863 } else {
864 temp &= 0xFFF1FFF1;
865 }
866
867 GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
868
869 return 0;
870 }
871
872 static int galmpsc_enter_hunt (int mpsc)
873 {
874 int temp;
875
876 temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
877 temp |= 0x80000000;
878 GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
879
880 while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
881 MPSC_ENTER_HUNT) {
882 udelay (1);
883 }
884 return 0;
885 }
886
887
888 static int galmpsc_shutdown (int mpsc)
889 {
890 unsigned int temp;
891
892 /* cause RX abort (clears RX) */
893 temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
894 temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
895 temp &= ~MPSC_ENTER_HUNT;
896 GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
897
898 GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
899 GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
900
901 /* shut down the MPSC */
902 GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
903 GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
904 GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
905
906 udelay (100);
907
908 /* shut down the sdma engines. */
909 /* reset config to default */
910 GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
911
912 udelay (100);
913
914 /* clear the SDMA current and first TX and RX pointers */
915 GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
916 GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
917 GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
918
919 udelay (100);
920
921 return 0;
922 }
923
924 static void galsdma_enable_rx (void)
925 {
926 int temp;
927
928 /* Enable RX processing */
929 temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
930 temp |= RX_ENABLE;
931 GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
932
933 galmpsc_enter_hunt (CHANNEL);
934 }
935
936 static int galmpsc_set_snoop (int mpsc, int value)
937 {
938 int reg =
939 mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
940 MPSC_0_ADDRESS_CONTROL_LOW;
941 int temp = GTREGREAD (reg);
942
943 if (value)
944 temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
945 else
946 temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
947 GT_REG_WRITE (reg, temp);
948 return 0;
949 }
950
951 /*******************************************************************************
952 * galsdma_set_mem_space - Set MV64360 IDMA memory decoding map.
953 *
954 * DESCRIPTION:
955 * the MV64360 SDMA has its own address decoding map that is de-coupled
956 * from the CPU interface address decoding windows. The SDMA channels
957 * share four address windows. Each region can be individually configured
958 * by this function by associating it to a target interface and setting
959 * base and size values.
960 *
961 * NOTE!!!
962 * The size must be in 64Kbyte granularity.
963 * The base address must be aligned to the size.
964 * The size must be a series of 1s followed by a series of zeros
965 *
966 * OUTPUT:
967 * None.
968 *
969 * RETURN:
970 * True for success, false otherwise.
971 *
972 *******************************************************************************/
973
974 static int galsdma_set_mem_space (unsigned int memSpace,
975 unsigned int memSpaceTarget,
976 unsigned int memSpaceAttr,
977 unsigned int baseAddress, unsigned int size)
978 {
979 unsigned int temp;
980
981 if (size == 0) {
982 GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
983 1 << memSpace);
984 return true;
985 }
986
987 /* The base address must be aligned to the size. */
988 if (baseAddress % size != 0) {
989 return false;
990 }
991 if (size < 0x10000) {
992 return false;
993 }
994
995 /* Align size and base to 64K */
996 baseAddress &= 0xffff0000;
997 size &= 0xffff0000;
998 temp = size >> 16;
999
1000 /* Checking that the size is a sequence of '1' followed by a
1001 sequence of '0' starting from LSB to MSB. */
1002 while ((temp > 0) && (temp & 0x1)) {
1003 temp = temp >> 1;
1004 }
1005
1006 if (temp != 0) {
1007 GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
1008 (baseAddress | memSpaceTarget | memSpaceAttr));
1009 GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8),
1010 (size - 1) & 0xffff0000);
1011 GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
1012 1 << memSpace);
1013 } else {
1014 /* An invalid size was specified */
1015 return false;
1016 }
1017 return true;
1018 }
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