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1 /*
2 * (C) Copyright 2003
3 * Ingo Assmus <ingo.assmus@keymile.com>
4 *
5 * based on - Driver for MV64360X ethernet ports
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27 /*
28 * mv_eth.c - header file for the polled mode GT ethernet driver
29 */
30 #include <common.h>
31 #include <net.h>
32 #include <malloc.h>
33
34 #include "mv_eth.h"
35
36 /* enable Debug outputs */
37
38 #undef DEBUG_MV_ETH
39
40 #ifdef DEBUG_MV_ETH
41 #define DEBUG
42 #define DP(x) x
43 #else
44 #define DP(x)
45 #endif
46
47 #undef MV64360_CHECKSUM_OFFLOAD
48 /*************************************************************************
49 **************************************************************************
50 **************************************************************************
51 * The first part is the high level driver of the gigE ethernet ports. *
52 **************************************************************************
53 **************************************************************************
54 *************************************************************************/
55
56 /* Definition for configuring driver */
57 /* #define UPDATE_STATS_BY_SOFTWARE */
58 #undef MV64360_RX_QUEUE_FILL_ON_TASK
59
60
61 /* Constants */
62 #define MAGIC_ETH_RUNNING 8031971
63 #define MV64360_INTERNAL_SRAM_SIZE _256K
64 #define EXTRA_BYTES 32
65 #define WRAP ETH_HLEN + 2 + 4 + 16
66 #define BUFFER_MTU dev->mtu + WRAP
67 #define INT_CAUSE_UNMASK_ALL 0x0007ffff
68 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
69 #ifdef MV64360_RX_FILL_ON_TASK
70 #define INT_CAUSE_MASK_ALL 0x00000000
71 #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
72 #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
73 #endif
74
75 /* Read/Write to/from MV64360 internal registers */
76 #define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
77 #define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
78 #define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
79 #define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
80
81 /* Static function declarations */
82 static int mv64360_eth_real_open (struct eth_device *eth);
83 static int mv64360_eth_real_stop (struct eth_device *eth);
84 static struct net_device_stats *mv64360_eth_get_stats (struct eth_device
85 *dev);
86 static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
87 static void mv64360_eth_update_stat (struct eth_device *dev);
88 bool db64360_eth_start (struct eth_device *eth);
89 unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
90 unsigned int mib_offset);
91 int mv64360_eth_receive (struct eth_device *dev);
92
93 int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
94
95 #ifndef UPDATE_STATS_BY_SOFTWARE
96 static void mv64360_eth_print_stat (struct eth_device *dev);
97 #endif
98 /* Processes a received packet */
99 extern void NetReceive (volatile uchar *, int);
100
101 extern unsigned int INTERNAL_REG_BASE_ADDR;
102
103 /*************************************************
104 *Helper functions - used inside the driver only *
105 *************************************************/
106 #ifdef DEBUG_MV_ETH
107 void print_globals (struct eth_device *dev)
108 {
109 printf ("Ethernet PRINT_Globals-Debug function\n");
110 printf ("Base Address for ETH_PORT_INFO: %08x\n",
111 (unsigned int) dev->priv);
112 printf ("Base Address for mv64360_eth_priv: %08x\n",
113 (unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
114 port_private));
115
116 printf ("GT Internal Base Address: %08x\n",
117 INTERNAL_REG_BASE_ADDR);
118 printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE);
119 printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE);
120 printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n",
121 (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
122 p_rx_buffer_base[0],
123 (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32);
124 printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n",
125 (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
126 p_tx_buffer_base[0],
127 (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32);
128 }
129 #endif
130
131 #define my_cpu_to_le32(x) my_le32_to_cpu((x))
132
133 unsigned long my_le32_to_cpu (unsigned long x)
134 {
135 return (((x & 0x000000ffU) << 24) |
136 ((x & 0x0000ff00U) << 8) |
137 ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
138 }
139
140
141 /**********************************************************************
142 * mv64360_eth_print_phy_status
143 *
144 * Prints gigabit ethenret phy status
145 *
146 * Input : pointer to ethernet interface network device structure
147 * Output : N/A
148 **********************************************************************/
149
150 static void mv64360_eth_print_phy_status (struct eth_device *dev)
151 {
152 struct mv64360_eth_priv *port_private;
153 unsigned int port_num;
154 ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
155 unsigned int port_status, phy_reg_data;
156
157 port_private =
158 (struct mv64360_eth_priv *) ethernet_private->port_private;
159 port_num = port_private->port_num;
160
161 /* Check Link status on phy */
162 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
163 if (!(phy_reg_data & 0x20)) {
164 printf ("Ethernet port changed link status to DOWN\n");
165 } else {
166 port_status =
167 MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
168 printf ("Ethernet status port %d: Link up", port_num);
169 printf (", %s",
170 (port_status & BIT2) ? "Full Duplex" : "Half Duplex");
171 if (port_status & BIT4)
172 printf (", Speed 1 Gbps");
173 else
174 printf (", %s",
175 (port_status & BIT5) ? "Speed 100 Mbps" :
176 "Speed 10 Mbps");
177 printf ("\n");
178 }
179 }
180
181 /**********************************************************************
182 * u-boot entry functions for mv64360_eth
183 *
184 **********************************************************************/
185 int db64360_eth_probe (struct eth_device *dev)
186 {
187 return ((int) db64360_eth_start (dev));
188 }
189
190 int db64360_eth_poll (struct eth_device *dev)
191 {
192 return mv64360_eth_receive (dev);
193 }
194
195 int db64360_eth_transmit (struct eth_device *dev, volatile void *packet,
196 int length)
197 {
198 mv64360_eth_xmit (dev, packet, length);
199 return 0;
200 }
201
202 void db64360_eth_disable (struct eth_device *dev)
203 {
204 mv64360_eth_stop (dev);
205 }
206
207
208 void mv6436x_eth_initialize (bd_t * bis)
209 {
210 struct eth_device *dev;
211 ETH_PORT_INFO *ethernet_private;
212 struct mv64360_eth_priv *port_private;
213 int devnum, x, temp;
214 char *s, *e, buf[64];
215
216 for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
217 dev = calloc (sizeof (*dev), 1);
218 if (!dev) {
219 printf ("%s: mv_enet%d allocation failure, %s\n",
220 __FUNCTION__, devnum, "eth_device structure");
221 return;
222 }
223
224 /* must be less than NAMESIZE (16) */
225 sprintf (dev->name, "mv_enet%d", devnum);
226
227 #ifdef DEBUG
228 printf ("Initializing %s\n", dev->name);
229 #endif
230
231 /* Extract the MAC address from the environment */
232 switch (devnum) {
233 case 0:
234 s = "ethaddr";
235 break;
236
237 case 1:
238 s = "eth1addr";
239 break;
240
241 case 2:
242 s = "eth2addr";
243 break;
244
245 default: /* this should never happen */
246 printf ("%s: Invalid device number %d\n",
247 __FUNCTION__, devnum);
248 return;
249 }
250
251 temp = getenv_r (s, buf, sizeof (buf));
252 s = (temp > 0) ? buf : NULL;
253
254 #ifdef DEBUG
255 printf ("Setting MAC %d to %s\n", devnum, s);
256 #endif
257 for (x = 0; x < 6; ++x) {
258 dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
259 if (s)
260 s = (*e) ? e + 1 : e;
261 }
262 /* ronen - set the MAC addr in the HW */
263 eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
264
265 dev->init = (void *) db64360_eth_probe;
266 dev->halt = (void *) ethernet_phy_reset;
267 dev->send = (void *) db64360_eth_transmit;
268 dev->recv = (void *) db64360_eth_poll;
269
270 ethernet_private =
271 calloc (sizeof (*ethernet_private), 1);
272 dev->priv = (void *) ethernet_private;
273 if (!ethernet_private) {
274 printf ("%s: %s allocation failure, %s\n",
275 __FUNCTION__, dev->name,
276 "Private Device Structure");
277 free (dev);
278 return;
279 }
280 /* start with an zeroed ETH_PORT_INFO */
281 memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
282 memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
283
284 /* set pointer to memory for stats data structure etc... */
285 port_private =
286 calloc (sizeof (*ethernet_private), 1);
287 ethernet_private->port_private = (void *)port_private;
288 if (!port_private) {
289 printf ("%s: %s allocation failure, %s\n",
290 __FUNCTION__, dev->name,
291 "Port Private Device Structure");
292
293 free (ethernet_private);
294 free (dev);
295 return;
296 }
297
298 port_private->stats =
299 calloc (sizeof (struct net_device_stats), 1);
300 if (!port_private->stats) {
301 printf ("%s: %s allocation failure, %s\n",
302 __FUNCTION__, dev->name,
303 "Net stat Structure");
304
305 free (port_private);
306 free (ethernet_private);
307 free (dev);
308 return;
309 }
310 memset (ethernet_private->port_private, 0,
311 sizeof (struct mv64360_eth_priv));
312 switch (devnum) {
313 case 0:
314 ethernet_private->port_num = ETH_0;
315 break;
316 case 1:
317 ethernet_private->port_num = ETH_1;
318 break;
319 case 2:
320 ethernet_private->port_num = ETH_2;
321 break;
322 default:
323 printf ("Invalid device number %d\n", devnum);
324 break;
325 };
326
327 port_private->port_num = devnum;
328 /*
329 * Read MIB counter on the GT in order to reset them,
330 * then zero all the stats fields in memory
331 */
332 mv64360_eth_update_stat (dev);
333 memset (port_private->stats, 0,
334 sizeof (struct net_device_stats));
335 /* Extract the MAC address from the environment */
336 switch (devnum) {
337 case 0:
338 s = "ethaddr";
339 break;
340
341 case 1:
342 s = "eth1addr";
343 break;
344
345 case 2:
346 s = "eth2addr";
347 break;
348
349 default: /* this should never happen */
350 printf ("%s: Invalid device number %d\n",
351 __FUNCTION__, devnum);
352 return;
353 }
354
355 temp = getenv_r (s, buf, sizeof (buf));
356 s = (temp > 0) ? buf : NULL;
357
358 #ifdef DEBUG
359 printf ("Setting MAC %d to %s\n", devnum, s);
360 #endif
361 for (x = 0; x < 6; ++x) {
362 dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
363 if (s)
364 s = (*e) ? e + 1 : e;
365 }
366
367 DP (printf ("Allocating descriptor and buffer rings\n"));
368
369 ethernet_private->p_rx_desc_area_base[0] =
370 (ETH_RX_DESC *) memalign (16,
371 RX_DESC_ALIGNED_SIZE *
372 MV64360_RX_QUEUE_SIZE + 1);
373 ethernet_private->p_tx_desc_area_base[0] =
374 (ETH_TX_DESC *) memalign (16,
375 TX_DESC_ALIGNED_SIZE *
376 MV64360_TX_QUEUE_SIZE + 1);
377
378 ethernet_private->p_rx_buffer_base[0] =
379 (char *) memalign (16,
380 MV64360_RX_QUEUE_SIZE *
381 MV64360_TX_BUFFER_SIZE + 1);
382 ethernet_private->p_tx_buffer_base[0] =
383 (char *) memalign (16,
384 MV64360_RX_QUEUE_SIZE *
385 MV64360_TX_BUFFER_SIZE + 1);
386
387 #ifdef DEBUG_MV_ETH
388 /* DEBUG OUTPUT prints adresses of globals */
389 print_globals (dev);
390 #endif
391 eth_register (dev);
392
393 }
394 DP (printf ("%s: exit\n", __FUNCTION__));
395
396 }
397
398 /**********************************************************************
399 * mv64360_eth_open
400 *
401 * This function is called when openning the network device. The function
402 * should initialize all the hardware, initialize cyclic Rx/Tx
403 * descriptors chain and buffers and allocate an IRQ to the network
404 * device.
405 *
406 * Input : a pointer to the network device structure
407 * / / ronen - changed the output to match net/eth.c needs
408 * Output : nonzero of success , zero if fails.
409 * under construction
410 **********************************************************************/
411
412 int mv64360_eth_open (struct eth_device *dev)
413 {
414 return (mv64360_eth_real_open (dev));
415 }
416
417 /* Helper function for mv64360_eth_open */
418 static int mv64360_eth_real_open (struct eth_device *dev)
419 {
420
421 unsigned int queue;
422 ETH_PORT_INFO *ethernet_private;
423 struct mv64360_eth_priv *port_private;
424 unsigned int port_num;
425 u32 port_status, phy_reg_data;
426
427 ethernet_private = (ETH_PORT_INFO *) dev->priv;
428 /* ronen - when we update the MAC env params we only update dev->enetaddr
429 see ./net/eth.c eth_set_enetaddr() */
430 memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
431
432 port_private =
433 (struct mv64360_eth_priv *) ethernet_private->port_private;
434 port_num = port_private->port_num;
435
436 /* Stop RX Queues */
437 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
438 0x0000ff00);
439
440 /* Clear the ethernet port interrupts */
441 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
442 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
443
444 /* Unmask RX buffer and TX end interrupt */
445 MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num),
446 INT_CAUSE_UNMASK_ALL);
447
448 /* Unmask phy and link status changes interrupts */
449 MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
450 INT_CAUSE_UNMASK_ALL_EXT);
451
452 /* Set phy address of the port */
453 ethernet_private->port_phy_addr = 0x8 + port_num;
454
455 /* Activate the DMA channels etc */
456 eth_port_init (ethernet_private);
457
458
459 /* "Allocate" setup TX rings */
460
461 for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
462 unsigned int size;
463
464 port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE;
465 size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */
466 ethernet_private->tx_desc_area_size[queue] = size;
467
468 /* first clear desc area completely */
469 memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
470 0, ethernet_private->tx_desc_area_size[queue]);
471
472 /* initialize tx desc ring with low level driver */
473 if (ether_init_tx_desc_ring
474 (ethernet_private, ETH_Q0,
475 port_private->tx_ring_size[queue],
476 MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
477 (unsigned int) ethernet_private->
478 p_tx_desc_area_base[queue],
479 (unsigned int) ethernet_private->
480 p_tx_buffer_base[queue]) == false)
481 printf ("### Error initializing TX Ring\n");
482 }
483
484 /* "Allocate" setup RX rings */
485 for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
486 unsigned int size;
487
488 /* Meantime RX Ring are fixed - but must be configurable by user */
489 port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE;
490 size = (port_private->rx_ring_size[queue] *
491 RX_DESC_ALIGNED_SIZE);
492 ethernet_private->rx_desc_area_size[queue] = size;
493
494 /* first clear desc area completely */
495 memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
496 0, ethernet_private->rx_desc_area_size[queue]);
497 if ((ether_init_rx_desc_ring
498 (ethernet_private, ETH_Q0,
499 port_private->rx_ring_size[queue],
500 MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
501 (unsigned int) ethernet_private->
502 p_rx_desc_area_base[queue],
503 (unsigned int) ethernet_private->
504 p_rx_buffer_base[queue])) == false)
505 printf ("### Error initializing RX Ring\n");
506 }
507
508 eth_port_start (ethernet_private);
509
510 /* Set maximum receive buffer to 9700 bytes */
511 MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num),
512 (0x5 << 17) |
513 (MV_REG_READ
514 (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num))
515 & 0xfff1ffff));
516
517 /*
518 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
519 * disable the leaky bucket mechanism .
520 */
521
522 MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
523 port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
524
525 /* Check Link status on phy */
526 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
527 if (!(phy_reg_data & 0x20)) {
528 /* Reset PHY */
529 if ((ethernet_phy_reset (port_num)) != true) {
530 printf ("$$ Warnning: No link on port %d \n",
531 port_num);
532 return 0;
533 } else {
534 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
535 if (!(phy_reg_data & 0x20)) {
536 printf ("### Error: Phy is not active\n");
537 return 0;
538 }
539 }
540 } else {
541 mv64360_eth_print_phy_status (dev);
542 }
543 port_private->eth_running = MAGIC_ETH_RUNNING;
544 return 1;
545 }
546
547
548 static int mv64360_eth_free_tx_rings (struct eth_device *dev)
549 {
550 unsigned int queue;
551 ETH_PORT_INFO *ethernet_private;
552 struct mv64360_eth_priv *port_private;
553 unsigned int port_num;
554 volatile ETH_TX_DESC *p_tx_curr_desc;
555
556 ethernet_private = (ETH_PORT_INFO *) dev->priv;
557 port_private =
558 (struct mv64360_eth_priv *) ethernet_private->port_private;
559 port_num = port_private->port_num;
560
561 /* Stop Tx Queues */
562 MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
563 0x0000ff00);
564
565 /* Free TX rings */
566 DP (printf ("Clearing previously allocated TX queues... "));
567 for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
568 /* Free on TX rings */
569 for (p_tx_curr_desc =
570 ethernet_private->p_tx_desc_area_base[queue];
571 ((unsigned int) p_tx_curr_desc <= (unsigned int)
572 ethernet_private->p_tx_desc_area_base[queue] +
573 ethernet_private->tx_desc_area_size[queue]);
574 p_tx_curr_desc =
575 (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
576 TX_DESC_ALIGNED_SIZE)) {
577 /* this is inside for loop */
578 if (p_tx_curr_desc->return_info != 0) {
579 p_tx_curr_desc->return_info = 0;
580 DP (printf ("freed\n"));
581 }
582 }
583 DP (printf ("Done\n"));
584 }
585 return 0;
586 }
587
588 static int mv64360_eth_free_rx_rings (struct eth_device *dev)
589 {
590 unsigned int queue;
591 ETH_PORT_INFO *ethernet_private;
592 struct mv64360_eth_priv *port_private;
593 unsigned int port_num;
594 volatile ETH_RX_DESC *p_rx_curr_desc;
595
596 ethernet_private = (ETH_PORT_INFO *) dev->priv;
597 port_private =
598 (struct mv64360_eth_priv *) ethernet_private->port_private;
599 port_num = port_private->port_num;
600
601
602 /* Stop RX Queues */
603 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
604 0x0000ff00);
605
606 /* Free RX rings */
607 DP (printf ("Clearing previously allocated RX queues... "));
608 for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
609 /* Free preallocated skb's on RX rings */
610 for (p_rx_curr_desc =
611 ethernet_private->p_rx_desc_area_base[queue];
612 (((unsigned int) p_rx_curr_desc <
613 ((unsigned int) ethernet_private->
614 p_rx_desc_area_base[queue] +
615 ethernet_private->rx_desc_area_size[queue])));
616 p_rx_curr_desc =
617 (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
618 RX_DESC_ALIGNED_SIZE)) {
619 if (p_rx_curr_desc->return_info != 0) {
620 p_rx_curr_desc->return_info = 0;
621 DP (printf ("freed\n"));
622 }
623 }
624 DP (printf ("Done\n"));
625 }
626 return 0;
627 }
628
629 /**********************************************************************
630 * mv64360_eth_stop
631 *
632 * This function is used when closing the network device.
633 * It updates the hardware,
634 * release all memory that holds buffers and descriptors and release the IRQ.
635 * Input : a pointer to the device structure
636 * Output : zero if success , nonzero if fails
637 *********************************************************************/
638
639 int mv64360_eth_stop (struct eth_device *dev)
640 {
641 ETH_PORT_INFO *ethernet_private;
642 struct mv64360_eth_priv *port_private;
643 unsigned int port_num;
644
645 ethernet_private = (ETH_PORT_INFO *) dev->priv;
646 port_private =
647 (struct mv64360_eth_priv *) ethernet_private->port_private;
648 port_num = port_private->port_num;
649
650 /* Disable all gigE address decoder */
651 MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
652 DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
653 mv64360_eth_real_stop (dev);
654
655 return 0;
656 };
657
658 /* Helper function for mv64360_eth_stop */
659
660 static int mv64360_eth_real_stop (struct eth_device *dev)
661 {
662 ETH_PORT_INFO *ethernet_private;
663 struct mv64360_eth_priv *port_private;
664 unsigned int port_num;
665
666 ethernet_private = (ETH_PORT_INFO *) dev->priv;
667 port_private =
668 (struct mv64360_eth_priv *) ethernet_private->port_private;
669 port_num = port_private->port_num;
670
671
672 mv64360_eth_free_tx_rings (dev);
673 mv64360_eth_free_rx_rings (dev);
674
675 eth_port_reset (ethernet_private->port_num);
676 /* Disable ethernet port interrupts */
677 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
678 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
679 /* Mask RX buffer and TX end interrupt */
680 MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0);
681 /* Mask phy and link status changes interrupts */
682 MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
683 MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH,
684 BIT0 << port_num);
685 /* Print Network statistics */
686 #ifndef UPDATE_STATS_BY_SOFTWARE
687 /*
688 * Print statistics (only if ethernet is running),
689 * then zero all the stats fields in memory
690 */
691 if (port_private->eth_running == MAGIC_ETH_RUNNING) {
692 port_private->eth_running = 0;
693 mv64360_eth_print_stat (dev);
694 }
695 memset (port_private->stats, 0, sizeof (struct net_device_stats));
696 #endif
697 DP (printf ("\nEthernet stopped ... \n"));
698 return 0;
699 }
700
701
702 /**********************************************************************
703 * mv64360_eth_start_xmit
704 *
705 * This function is queues a packet in the Tx descriptor for
706 * required port.
707 *
708 * Input : skb - a pointer to socket buffer
709 * dev - a pointer to the required port
710 *
711 * Output : zero upon success
712 **********************************************************************/
713
714 int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
715 int dataSize)
716 {
717 ETH_PORT_INFO *ethernet_private;
718 struct mv64360_eth_priv *port_private;
719 unsigned int port_num;
720 PKT_INFO pkt_info;
721 ETH_FUNC_RET_STATUS status;
722 struct net_device_stats *stats;
723 ETH_FUNC_RET_STATUS release_result;
724
725 ethernet_private = (ETH_PORT_INFO *) dev->priv;
726 port_private =
727 (struct mv64360_eth_priv *) ethernet_private->port_private;
728 port_num = port_private->port_num;
729
730 stats = port_private->stats;
731
732 /* Update packet info data structure */
733 pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */
734 pkt_info.byte_cnt = dataSize;
735 pkt_info.buf_ptr = (unsigned int) dataPtr;
736
737 status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
738 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
739 printf ("Error on transmitting packet ..");
740 if (status == ETH_QUEUE_FULL)
741 printf ("ETH Queue is full. \n");
742 if (status == ETH_QUEUE_LAST_RESOURCE)
743 printf ("ETH Queue: using last available resource. \n");
744 goto error;
745 }
746
747 /* Update statistics and start of transmittion time */
748 stats->tx_bytes += dataSize;
749 stats->tx_packets++;
750
751 /* Check if packet(s) is(are) transmitted correctly (release everything) */
752 do {
753 release_result =
754 eth_tx_return_desc (ethernet_private, ETH_Q0,
755 &pkt_info);
756 switch (release_result) {
757 case ETH_OK:
758 DP (printf ("descriptor released\n"));
759 if (pkt_info.cmd_sts & BIT0) {
760 printf ("Error in TX\n");
761 stats->tx_errors++;
762
763 }
764 break;
765 case ETH_RETRY:
766 DP (printf ("transmission still in process\n"));
767 break;
768
769 case ETH_ERROR:
770 printf ("routine can not access Tx desc ring\n");
771 break;
772
773 case ETH_END_OF_JOB:
774 DP (printf ("the routine has nothing to release\n"));
775 break;
776 default: /* should not happen */
777 break;
778 }
779 } while (release_result == ETH_OK);
780
781
782 return 0; /* success */
783 error:
784 return 1; /* Failed - higher layers will free the skb */
785 }
786
787 /**********************************************************************
788 * mv64360_eth_receive
789 *
790 * This function is forward packets that are received from the port's
791 * queues toward kernel core or FastRoute them to another interface.
792 *
793 * Input : dev - a pointer to the required interface
794 * max - maximum number to receive (0 means unlimted)
795 *
796 * Output : number of served packets
797 **********************************************************************/
798
799 int mv64360_eth_receive (struct eth_device *dev)
800 {
801 ETH_PORT_INFO *ethernet_private;
802 struct mv64360_eth_priv *port_private;
803 unsigned int port_num;
804 PKT_INFO pkt_info;
805 struct net_device_stats *stats;
806
807
808 ethernet_private = (ETH_PORT_INFO *) dev->priv;
809 port_private =
810 (struct mv64360_eth_priv *) ethernet_private->port_private;
811 port_num = port_private->port_num;
812 stats = port_private->stats;
813
814 while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
815 ETH_OK)) {
816
817 #ifdef DEBUG_MV_ETH
818 if (pkt_info.byte_cnt != 0) {
819 printf ("%s: Received %d byte Packet @ 0x%x\n",
820 __FUNCTION__, pkt_info.byte_cnt,
821 pkt_info.buf_ptr);
822 }
823 #endif
824 /* Update statistics. Note byte count includes 4 byte CRC count */
825 stats->rx_packets++;
826 stats->rx_bytes += pkt_info.byte_cnt;
827
828 /*
829 * In case received a packet without first / last bits on OR the error
830 * summary bit is on, the packets needs to be dropeed.
831 */
832 if (((pkt_info.
833 cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
834 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
835 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
836 stats->rx_dropped++;
837
838 printf ("Received packet spread on multiple descriptors\n");
839
840 /* Is this caused by an error ? */
841 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
842 stats->rx_errors++;
843 }
844
845 /* free these descriptors again without forwarding them to the higher layers */
846 pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
847 pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
848
849 if (eth_rx_return_buff
850 (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
851 printf ("Error while returning the RX Desc to Ring\n");
852 } else {
853 DP (printf ("RX Desc returned to Ring\n"));
854 }
855 /* /free these descriptors again */
856 } else {
857
858 /* !!! call higher layer processing */
859 #ifdef DEBUG_MV_ETH
860 printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
861 #endif
862 /* let the upper layer handle the packet */
863 NetReceive ((uchar *) pkt_info.buf_ptr,
864 (int) pkt_info.byte_cnt);
865
866 /* **************************************************************** */
867 /* free descriptor */
868 pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
869 pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
870 DP (printf
871 ("RX: pkt_info.buf_ptr = %x\n",
872 pkt_info.buf_ptr));
873 if (eth_rx_return_buff
874 (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
875 printf ("Error while returning the RX Desc to Ring\n");
876 } else {
877 DP (printf ("RX Desc returned to Ring\n"));
878 }
879
880 /* **************************************************************** */
881
882 }
883 }
884 mv64360_eth_get_stats (dev); /* update statistics */
885 return 1;
886 }
887
888 /**********************************************************************
889 * mv64360_eth_get_stats
890 *
891 * Returns a pointer to the interface statistics.
892 *
893 * Input : dev - a pointer to the required interface
894 *
895 * Output : a pointer to the interface's statistics
896 **********************************************************************/
897
898 static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev)
899 {
900 ETH_PORT_INFO *ethernet_private;
901 struct mv64360_eth_priv *port_private;
902 unsigned int port_num;
903
904 ethernet_private = (ETH_PORT_INFO *) dev->priv;
905 port_private =
906 (struct mv64360_eth_priv *) ethernet_private->port_private;
907 port_num = port_private->port_num;
908
909 mv64360_eth_update_stat (dev);
910
911 return port_private->stats;
912 }
913
914
915 /**********************************************************************
916 * mv64360_eth_update_stat
917 *
918 * Update the statistics structure in the private data structure
919 *
920 * Input : pointer to ethernet interface network device structure
921 * Output : N/A
922 **********************************************************************/
923
924 static void mv64360_eth_update_stat (struct eth_device *dev)
925 {
926 ETH_PORT_INFO *ethernet_private;
927 struct mv64360_eth_priv *port_private;
928 struct net_device_stats *stats;
929 unsigned int port_num;
930 volatile unsigned int dummy;
931
932 ethernet_private = (ETH_PORT_INFO *) dev->priv;
933 port_private =
934 (struct mv64360_eth_priv *) ethernet_private->port_private;
935 port_num = port_private->port_num;
936 stats = port_private->stats;
937
938 /* These are false updates */
939 stats->rx_packets += (unsigned long)
940 eth_read_mib_counter (ethernet_private->port_num,
941 ETH_MIB_GOOD_FRAMES_RECEIVED);
942 stats->tx_packets += (unsigned long)
943 eth_read_mib_counter (ethernet_private->port_num,
944 ETH_MIB_GOOD_FRAMES_SENT);
945 stats->rx_bytes += (unsigned long)
946 eth_read_mib_counter (ethernet_private->port_num,
947 ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
948 /*
949 * Ideally this should be as follows -
950 *
951 * stats->rx_bytes += stats->rx_bytes +
952 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
953 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
954 *
955 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
956 * is just a dummy read for proper work of the GigE port
957 */
958 dummy = eth_read_mib_counter (ethernet_private->port_num,
959 ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
960 stats->tx_bytes += (unsigned long)
961 eth_read_mib_counter (ethernet_private->port_num,
962 ETH_MIB_GOOD_OCTETS_SENT_LOW);
963 dummy = eth_read_mib_counter (ethernet_private->port_num,
964 ETH_MIB_GOOD_OCTETS_SENT_HIGH);
965 stats->rx_errors += (unsigned long)
966 eth_read_mib_counter (ethernet_private->port_num,
967 ETH_MIB_MAC_RECEIVE_ERROR);
968
969 /* Rx dropped is for received packet with CRC error */
970 stats->rx_dropped +=
971 (unsigned long) eth_read_mib_counter (ethernet_private->
972 port_num,
973 ETH_MIB_BAD_CRC_EVENT);
974 stats->multicast += (unsigned long)
975 eth_read_mib_counter (ethernet_private->port_num,
976 ETH_MIB_MULTICAST_FRAMES_RECEIVED);
977 stats->collisions +=
978 (unsigned long) eth_read_mib_counter (ethernet_private->
979 port_num,
980 ETH_MIB_COLLISION) +
981 (unsigned long) eth_read_mib_counter (ethernet_private->
982 port_num,
983 ETH_MIB_LATE_COLLISION);
984 /* detailed rx errors */
985 stats->rx_length_errors +=
986 (unsigned long) eth_read_mib_counter (ethernet_private->
987 port_num,
988 ETH_MIB_UNDERSIZE_RECEIVED)
989 +
990 (unsigned long) eth_read_mib_counter (ethernet_private->
991 port_num,
992 ETH_MIB_OVERSIZE_RECEIVED);
993 /* detailed tx errors */
994 }
995
996 #ifndef UPDATE_STATS_BY_SOFTWARE
997 /**********************************************************************
998 * mv64360_eth_print_stat
999 *
1000 * Update the statistics structure in the private data structure
1001 *
1002 * Input : pointer to ethernet interface network device structure
1003 * Output : N/A
1004 **********************************************************************/
1005
1006 static void mv64360_eth_print_stat (struct eth_device *dev)
1007 {
1008 ETH_PORT_INFO *ethernet_private;
1009 struct mv64360_eth_priv *port_private;
1010 struct net_device_stats *stats;
1011 unsigned int port_num;
1012
1013 ethernet_private = (ETH_PORT_INFO *) dev->priv;
1014 port_private =
1015 (struct mv64360_eth_priv *) ethernet_private->port_private;
1016 port_num = port_private->port_num;
1017 stats = port_private->stats;
1018
1019 /* These are false updates */
1020 printf ("\n### Network statistics: ###\n");
1021 printf ("--------------------------\n");
1022 printf (" Packets received: %ld\n", stats->rx_packets);
1023 printf (" Packets send: %ld\n", stats->tx_packets);
1024 printf (" Received bytes: %ld\n", stats->rx_bytes);
1025 printf (" Send bytes: %ld\n", stats->tx_bytes);
1026 if (stats->rx_errors != 0)
1027 printf (" Rx Errors: %ld\n",
1028 stats->rx_errors);
1029 if (stats->rx_dropped != 0)
1030 printf (" Rx dropped (CRC Errors): %ld\n",
1031 stats->rx_dropped);
1032 if (stats->multicast != 0)
1033 printf (" Rx mulicast frames: %ld\n",
1034 stats->multicast);
1035 if (stats->collisions != 0)
1036 printf (" No. of collisions: %ld\n",
1037 stats->collisions);
1038 if (stats->rx_length_errors != 0)
1039 printf (" Rx length errors: %ld\n",
1040 stats->rx_length_errors);
1041 }
1042 #endif
1043
1044 /**************************************************************************
1045 *network_start - Network Kick Off Routine UBoot
1046 *Inputs :
1047 *Outputs :
1048 **************************************************************************/
1049
1050 bool db64360_eth_start (struct eth_device *dev)
1051 {
1052 return (mv64360_eth_open (dev)); /* calls real open */
1053 }
1054
1055 /*************************************************************************
1056 **************************************************************************
1057 **************************************************************************
1058 * The second part is the low level driver of the gigE ethernet ports. *
1059 **************************************************************************
1060 **************************************************************************
1061 *************************************************************************/
1062 /*
1063 * based on Linux code
1064 * arch/ppc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
1065 * Copyright (C) 2002 rabeeh@galileo.co.il
1066
1067 * This program is free software; you can redistribute it and/or
1068 * modify it under the terms of the GNU General Public License
1069 * as published by the Free Software Foundation; either version 2
1070 * of the License, or (at your option) any later version.
1071
1072 * This program is distributed in the hope that it will be useful,
1073 * but WITHOUT ANY WARRANTY; without even the implied warranty of
1074 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1075 * GNU General Public License for more details.
1076
1077 * You should have received a copy of the GNU General Public License
1078 * along with this program; if not, write to the Free Software
1079 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
1080 *
1081 */
1082
1083 /********************************************************************************
1084 * Marvell's Gigabit Ethernet controller low level driver
1085 *
1086 * DESCRIPTION:
1087 * This file introduce low level API to Marvell's Gigabit Ethernet
1088 * controller. This Gigabit Ethernet Controller driver API controls
1089 * 1) Operations (i.e. port init, start, reset etc').
1090 * 2) Data flow (i.e. port send, receive etc').
1091 * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
1092 * struct.
1093 * This struct includes user configuration information as well as
1094 * driver internal data needed for its operations.
1095 *
1096 * Supported Features:
1097 * - This low level driver is OS independent. Allocating memory for
1098 * the descriptor rings and buffers are not within the scope of
1099 * this driver.
1100 * - The user is free from Rx/Tx queue managing.
1101 * - This low level driver introduce functionality API that enable
1102 * the to operate Marvell's Gigabit Ethernet Controller in a
1103 * convenient way.
1104 * - Simple Gigabit Ethernet port operation API.
1105 * - Simple Gigabit Ethernet port data flow API.
1106 * - Data flow and operation API support per queue functionality.
1107 * - Support cached descriptors for better performance.
1108 * - Enable access to all four DRAM banks and internal SRAM memory
1109 * spaces.
1110 * - PHY access and control API.
1111 * - Port control register configuration API.
1112 * - Full control over Unicast and Multicast MAC configurations.
1113 *
1114 * Operation flow:
1115 *
1116 * Initialization phase
1117 * This phase complete the initialization of the ETH_PORT_INFO
1118 * struct.
1119 * User information regarding port configuration has to be set
1120 * prior to calling the port initialization routine. For example,
1121 * the user has to assign the port_phy_addr field which is board
1122 * depended parameter.
1123 * In this phase any port Tx/Rx activity is halted, MIB counters
1124 * are cleared, PHY address is set according to user parameter and
1125 * access to DRAM and internal SRAM memory spaces.
1126 *
1127 * Driver ring initialization
1128 * Allocating memory for the descriptor rings and buffers is not
1129 * within the scope of this driver. Thus, the user is required to
1130 * allocate memory for the descriptors ring and buffers. Those
1131 * memory parameters are used by the Rx and Tx ring initialization
1132 * routines in order to curve the descriptor linked list in a form
1133 * of a ring.
1134 * Note: Pay special attention to alignment issues when using
1135 * cached descriptors/buffers. In this phase the driver store
1136 * information in the ETH_PORT_INFO struct regarding each queue
1137 * ring.
1138 *
1139 * Driver start
1140 * This phase prepares the Ethernet port for Rx and Tx activity.
1141 * It uses the information stored in the ETH_PORT_INFO struct to
1142 * initialize the various port registers.
1143 *
1144 * Data flow:
1145 * All packet references to/from the driver are done using PKT_INFO
1146 * struct.
1147 * This struct is a unified struct used with Rx and Tx operations.
1148 * This way the user is not required to be familiar with neither
1149 * Tx nor Rx descriptors structures.
1150 * The driver's descriptors rings are management by indexes.
1151 * Those indexes controls the ring resources and used to indicate
1152 * a SW resource error:
1153 * 'current'
1154 * This index points to the current available resource for use. For
1155 * example in Rx process this index will point to the descriptor
1156 * that will be passed to the user upon calling the receive routine.
1157 * In Tx process, this index will point to the descriptor
1158 * that will be assigned with the user packet info and transmitted.
1159 * 'used'
1160 * This index points to the descriptor that need to restore its
1161 * resources. For example in Rx process, using the Rx buffer return
1162 * API will attach the buffer returned in packet info to the
1163 * descriptor pointed by 'used'. In Tx process, using the Tx
1164 * descriptor return will merely return the user packet info with
1165 * the command status of the transmitted buffer pointed by the
1166 * 'used' index. Nevertheless, it is essential to use this routine
1167 * to update the 'used' index.
1168 * 'first'
1169 * This index supports Tx Scatter-Gather. It points to the first
1170 * descriptor of a packet assembled of multiple buffers. For example
1171 * when in middle of Such packet we have a Tx resource error the
1172 * 'curr' index get the value of 'first' to indicate that the ring
1173 * returned to its state before trying to transmit this packet.
1174 *
1175 * Receive operation:
1176 * The eth_port_receive API set the packet information struct,
1177 * passed by the caller, with received information from the
1178 * 'current' SDMA descriptor.
1179 * It is the user responsibility to return this resource back
1180 * to the Rx descriptor ring to enable the reuse of this source.
1181 * Return Rx resource is done using the eth_rx_return_buff API.
1182 *
1183 * Transmit operation:
1184 * The eth_port_send API supports Scatter-Gather which enables to
1185 * send a packet spanned over multiple buffers. This means that
1186 * for each packet info structure given by the user and put into
1187 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1188 * bit will be set in the packet info command status field. This
1189 * API also consider restriction regarding buffer alignments and
1190 * sizes.
1191 * The user must return a Tx resource after ensuring the buffer
1192 * has been transmitted to enable the Tx ring indexes to update.
1193 *
1194 * BOARD LAYOUT
1195 * This device is on-board. No jumper diagram is necessary.
1196 *
1197 * EXTERNAL INTERFACE
1198 *
1199 * Prior to calling the initialization routine eth_port_init() the user
1200 * must set the following fields under ETH_PORT_INFO struct:
1201 * port_num User Ethernet port number.
1202 * port_phy_addr User PHY address of Ethernet port.
1203 * port_mac_addr[6] User defined port MAC address.
1204 * port_config User port configuration value.
1205 * port_config_extend User port config extend value.
1206 * port_sdma_config User port SDMA config value.
1207 * port_serial_control User port serial control value.
1208 * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr.
1209 * *port_private User scratch pad for user specific data structures.
1210 *
1211 * This driver introduce a set of default values:
1212 * PORT_CONFIG_VALUE Default port configuration value
1213 * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value
1214 * PORT_SDMA_CONFIG_VALUE Default sdma control value
1215 * PORT_SERIAL_CONTROL_VALUE Default port serial control value
1216 *
1217 * This driver data flow is done using the PKT_INFO struct which is
1218 * a unified struct for Rx and Tx operations:
1219 * byte_cnt Tx/Rx descriptor buffer byte count.
1220 * l4i_chk CPU provided TCP Checksum. For Tx operation only.
1221 * cmd_sts Tx/Rx descriptor command status.
1222 * buf_ptr Tx/Rx descriptor buffer pointer.
1223 * return_info Tx/Rx user resource return information.
1224 *
1225 *
1226 * EXTERNAL SUPPORT REQUIREMENTS
1227 *
1228 * This driver requires the following external support:
1229 *
1230 * D_CACHE_FLUSH_LINE (address, address offset)
1231 *
1232 * This macro applies assembly code to flush and invalidate cache
1233 * line.
1234 * address - address base.
1235 * address offset - address offset
1236 *
1237 *
1238 * CPU_PIPE_FLUSH
1239 *
1240 * This macro applies assembly code to flush the CPU pipeline.
1241 *
1242 *******************************************************************************/
1243 /* includes */
1244
1245 /* defines */
1246 /* SDMA command macros */
1247 #define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
1248 MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
1249
1250 #define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
1251 MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
1252 (1 << (8 + tx_queue)))
1253
1254 #define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
1255 MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
1256
1257 #define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
1258 MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
1259
1260 #define CURR_RFD_GET(p_curr_desc, queue) \
1261 ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
1262
1263 #define CURR_RFD_SET(p_curr_desc, queue) \
1264 (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
1265
1266 #define USED_RFD_GET(p_used_desc, queue) \
1267 ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
1268
1269 #define USED_RFD_SET(p_used_desc, queue)\
1270 (p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
1271
1272
1273 #define CURR_TFD_GET(p_curr_desc, queue) \
1274 ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
1275
1276 #define CURR_TFD_SET(p_curr_desc, queue) \
1277 (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
1278
1279 #define USED_TFD_GET(p_used_desc, queue) \
1280 ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
1281
1282 #define USED_TFD_SET(p_used_desc, queue) \
1283 (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
1284
1285 #define FIRST_TFD_GET(p_first_desc, queue) \
1286 ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
1287
1288 #define FIRST_TFD_SET(p_first_desc, queue) \
1289 (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
1290
1291
1292 /* Macros that save access to desc in order to find next desc pointer */
1293 #define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
1294
1295 #define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
1296
1297 #define LINK_UP_TIMEOUT 100000
1298 #define PHY_BUSY_TIMEOUT 10000000
1299
1300 /* locals */
1301
1302 /* PHY routines */
1303 static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
1304 static int ethernet_phy_get (ETH_PORT eth_port_num);
1305
1306 /* Ethernet Port routines */
1307 static void eth_set_access_control (ETH_PORT eth_port_num,
1308 ETH_WIN_PARAM * param);
1309 static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
1310 ETH_QUEUE queue, int option);
1311 #if 0 /* FIXME */
1312 static bool eth_port_smc_addr (ETH_PORT eth_port_num,
1313 unsigned char mc_byte,
1314 ETH_QUEUE queue, int option);
1315 static bool eth_port_omc_addr (ETH_PORT eth_port_num,
1316 unsigned char crc8,
1317 ETH_QUEUE queue, int option);
1318 #endif
1319
1320 static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
1321 int byte_count);
1322
1323 void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
1324
1325
1326 typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
1327 u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
1328 {
1329 u32 result = 0;
1330 u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
1331
1332 if (enable & (1 << bank))
1333 return 0;
1334 if (bank == BANK0)
1335 result = MV_REG_READ (MV64360_CS_0_BASE_ADDR);
1336 if (bank == BANK1)
1337 result = MV_REG_READ (MV64360_CS_1_BASE_ADDR);
1338 if (bank == BANK2)
1339 result = MV_REG_READ (MV64360_CS_2_BASE_ADDR);
1340 if (bank == BANK3)
1341 result = MV_REG_READ (MV64360_CS_3_BASE_ADDR);
1342 result &= 0x0000ffff;
1343 result = result << 16;
1344 return result;
1345 }
1346
1347 u32 mv_get_dram_bank_size (MEMORY_BANK bank)
1348 {
1349 u32 result = 0;
1350 u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
1351
1352 if (enable & (1 << bank))
1353 return 0;
1354 if (bank == BANK0)
1355 result = MV_REG_READ (MV64360_CS_0_SIZE);
1356 if (bank == BANK1)
1357 result = MV_REG_READ (MV64360_CS_1_SIZE);
1358 if (bank == BANK2)
1359 result = MV_REG_READ (MV64360_CS_2_SIZE);
1360 if (bank == BANK3)
1361 result = MV_REG_READ (MV64360_CS_3_SIZE);
1362 result += 1;
1363 result &= 0x0000ffff;
1364 result = result << 16;
1365 return result;
1366 }
1367
1368 u32 mv_get_internal_sram_base (void)
1369 {
1370 u32 result;
1371
1372 result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR);
1373 result &= 0x0000ffff;
1374 result = result << 16;
1375 return result;
1376 }
1377
1378 /*******************************************************************************
1379 * eth_port_init - Initialize the Ethernet port driver
1380 *
1381 * DESCRIPTION:
1382 * This function prepares the ethernet port to start its activity:
1383 * 1) Completes the ethernet port driver struct initialization toward port
1384 * start routine.
1385 * 2) Resets the device to a quiescent state in case of warm reboot.
1386 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1387 * 4) Clean MAC tables. The reset status of those tables is unknown.
1388 * 5) Set PHY address.
1389 * Note: Call this routine prior to eth_port_start routine and after setting
1390 * user values in the user fields of Ethernet port control struct (i.e.
1391 * port_phy_addr).
1392 *
1393 * INPUT:
1394 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
1395 *
1396 * OUTPUT:
1397 * See description.
1398 *
1399 * RETURN:
1400 * None.
1401 *
1402 *******************************************************************************/
1403 static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
1404 {
1405 int queue;
1406 ETH_WIN_PARAM win_param;
1407
1408 p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
1409 p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
1410 p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
1411 p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
1412
1413 p_eth_port_ctrl->port_rx_queue_command = 0;
1414 p_eth_port_ctrl->port_tx_queue_command = 0;
1415
1416 /* Zero out SW structs */
1417 for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
1418 CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
1419 USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
1420 p_eth_port_ctrl->rx_resource_err[queue] = false;
1421 }
1422
1423 for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
1424 CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1425 USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1426 FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1427 p_eth_port_ctrl->tx_resource_err[queue] = false;
1428 }
1429
1430 eth_port_reset (p_eth_port_ctrl->port_num);
1431
1432 /* Set access parameters for DRAM bank 0 */
1433 win_param.win = ETH_WIN0; /* Use Ethernet window 0 */
1434 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1435 win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */
1436 #ifndef CONFIG_NOT_COHERENT_CACHE
1437 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1438 #endif
1439 win_param.high_addr = 0;
1440 /* Get bank base */
1441 win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
1442 win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
1443 if (win_param.size == 0)
1444 win_param.enable = 0;
1445 else
1446 win_param.enable = 1; /* Enable the access */
1447 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1448
1449 /* Set the access control for address window (EPAPR) READ & WRITE */
1450 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1451
1452 /* Set access parameters for DRAM bank 1 */
1453 win_param.win = ETH_WIN1; /* Use Ethernet window 1 */
1454 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1455 win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */
1456 #ifndef CONFIG_NOT_COHERENT_CACHE
1457 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1458 #endif
1459 win_param.high_addr = 0;
1460 /* Get bank base */
1461 win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
1462 win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
1463 if (win_param.size == 0)
1464 win_param.enable = 0;
1465 else
1466 win_param.enable = 1; /* Enable the access */
1467 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1468
1469 /* Set the access control for address window (EPAPR) READ & WRITE */
1470 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1471
1472 /* Set access parameters for DRAM bank 2 */
1473 win_param.win = ETH_WIN2; /* Use Ethernet window 2 */
1474 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1475 win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */
1476 #ifndef CONFIG_NOT_COHERENT_CACHE
1477 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1478 #endif
1479 win_param.high_addr = 0;
1480 /* Get bank base */
1481 win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
1482 win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
1483 if (win_param.size == 0)
1484 win_param.enable = 0;
1485 else
1486 win_param.enable = 1; /* Enable the access */
1487 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1488
1489 /* Set the access control for address window (EPAPR) READ & WRITE */
1490 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1491
1492 /* Set access parameters for DRAM bank 3 */
1493 win_param.win = ETH_WIN3; /* Use Ethernet window 3 */
1494 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1495 win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */
1496 #ifndef CONFIG_NOT_COHERENT_CACHE
1497 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1498 #endif
1499 win_param.high_addr = 0;
1500 /* Get bank base */
1501 win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
1502 win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
1503 if (win_param.size == 0)
1504 win_param.enable = 0;
1505 else
1506 win_param.enable = 1; /* Enable the access */
1507 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1508
1509 /* Set the access control for address window (EPAPR) READ & WRITE */
1510 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1511
1512 /* Set access parameters for Internal SRAM */
1513 win_param.win = ETH_WIN4; /* Use Ethernet window 0 */
1514 win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */
1515 win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
1516 win_param.high_addr = 0;
1517 win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */
1518 win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */
1519 win_param.enable = 1; /* Enable the access */
1520 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1521
1522 /* Set the access control for address window (EPAPR) READ & WRITE */
1523 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1524
1525 eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
1526
1527 ethernet_phy_set (p_eth_port_ctrl->port_num,
1528 p_eth_port_ctrl->port_phy_addr);
1529
1530 return;
1531
1532 }
1533
1534 /*******************************************************************************
1535 * eth_port_start - Start the Ethernet port activity.
1536 *
1537 * DESCRIPTION:
1538 * This routine prepares the Ethernet port for Rx and Tx activity:
1539 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1540 * has been initialized a descriptor's ring (using ether_init_tx_desc_ring
1541 * for Tx and ether_init_rx_desc_ring for Rx)
1542 * 2. Initialize and enable the Ethernet configuration port by writing to
1543 * the port's configuration and command registers.
1544 * 3. Initialize and enable the SDMA by writing to the SDMA's
1545 * configuration and command registers.
1546 * After completing these steps, the ethernet port SDMA can starts to
1547 * perform Rx and Tx activities.
1548 *
1549 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1550 * to calling this function (use ether_init_tx_desc_ring for Tx queues and
1551 * ether_init_rx_desc_ring for Rx queues).
1552 *
1553 * INPUT:
1554 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
1555 *
1556 * OUTPUT:
1557 * Ethernet port is ready to receive and transmit.
1558 *
1559 * RETURN:
1560 * false if the port PHY is not up.
1561 * true otherwise.
1562 *
1563 *******************************************************************************/
1564 static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
1565 {
1566 int queue;
1567 volatile ETH_TX_DESC *p_tx_curr_desc;
1568 volatile ETH_RX_DESC *p_rx_curr_desc;
1569 unsigned int phy_reg_data;
1570 ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
1571
1572
1573 /* Assignment of Tx CTRP of given queue */
1574 for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
1575 CURR_TFD_GET (p_tx_curr_desc, queue);
1576 MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
1577 (eth_port_num)
1578 + (4 * queue)),
1579 ((unsigned int) p_tx_curr_desc));
1580
1581 }
1582
1583 /* Assignment of Rx CRDP of given queue */
1584 for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
1585 CURR_RFD_GET (p_rx_curr_desc, queue);
1586 MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
1587 (eth_port_num)
1588 + (4 * queue)),
1589 ((unsigned int) p_rx_curr_desc));
1590
1591 if (p_rx_curr_desc != NULL)
1592 /* Add the assigned Ethernet address to the port's address table */
1593 eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
1594 p_eth_port_ctrl->port_mac_addr,
1595 queue);
1596 }
1597
1598 /* Assign port configuration and command. */
1599 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
1600 p_eth_port_ctrl->port_config);
1601
1602 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
1603 p_eth_port_ctrl->port_config_extend);
1604
1605 MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
1606 p_eth_port_ctrl->port_serial_control);
1607
1608 MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
1609 ETH_SERIAL_PORT_ENABLE);
1610
1611 /* Assign port SDMA configuration */
1612 MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
1613 p_eth_port_ctrl->port_sdma_config);
1614
1615 MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
1616 (eth_port_num), 0x3fffffff);
1617 MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
1618 (eth_port_num), 0x03fffcff);
1619 /* Turn off the port/queue bandwidth limitation */
1620 MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
1621
1622 /* Enable port Rx. */
1623 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
1624 p_eth_port_ctrl->port_rx_queue_command);
1625
1626 /* Check if link is up */
1627 eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
1628
1629 if (!(phy_reg_data & 0x20))
1630 return false;
1631
1632 return true;
1633 }
1634
1635 /*******************************************************************************
1636 * eth_port_uc_addr_set - This function Set the port Unicast address.
1637 *
1638 * DESCRIPTION:
1639 * This function Set the port Ethernet MAC address.
1640 *
1641 * INPUT:
1642 * ETH_PORT eth_port_num Port number.
1643 * char * p_addr Address to be set
1644 * ETH_QUEUE queue Rx queue number for this MAC address.
1645 *
1646 * OUTPUT:
1647 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1648 * To set the unicast table with the proper information.
1649 *
1650 * RETURN:
1651 * N/A.
1652 *
1653 *******************************************************************************/
1654 static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
1655 unsigned char *p_addr, ETH_QUEUE queue)
1656 {
1657 unsigned int mac_h;
1658 unsigned int mac_l;
1659
1660 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1661 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
1662 (p_addr[2] << 8) | (p_addr[3] << 0);
1663
1664 MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
1665 MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
1666
1667 /* Accept frames of this address */
1668 eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
1669
1670 return;
1671 }
1672
1673 /*******************************************************************************
1674 * eth_port_uc_addr - This function Set the port unicast address table
1675 *
1676 * DESCRIPTION:
1677 * This function locates the proper entry in the Unicast table for the
1678 * specified MAC nibble and sets its properties according to function
1679 * parameters.
1680 *
1681 * INPUT:
1682 * ETH_PORT eth_port_num Port number.
1683 * unsigned char uc_nibble Unicast MAC Address last nibble.
1684 * ETH_QUEUE queue Rx queue number for this MAC address.
1685 * int option 0 = Add, 1 = remove address.
1686 *
1687 * OUTPUT:
1688 * This function add/removes MAC addresses from the port unicast address
1689 * table.
1690 *
1691 * RETURN:
1692 * true is output succeeded.
1693 * false if option parameter is invalid.
1694 *
1695 *******************************************************************************/
1696 static bool eth_port_uc_addr (ETH_PORT eth_port_num,
1697 unsigned char uc_nibble,
1698 ETH_QUEUE queue, int option)
1699 {
1700 unsigned int unicast_reg;
1701 unsigned int tbl_offset;
1702 unsigned int reg_offset;
1703
1704 /* Locate the Unicast table entry */
1705 uc_nibble = (0xf & uc_nibble);
1706 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
1707 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
1708
1709 switch (option) {
1710 case REJECT_MAC_ADDR:
1711 /* Clear accepts frame bit at specified unicast DA table entry */
1712 unicast_reg =
1713 MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1714 (eth_port_num)
1715 + tbl_offset));
1716
1717 unicast_reg &= (0x0E << (8 * reg_offset));
1718
1719 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1720 (eth_port_num)
1721 + tbl_offset), unicast_reg);
1722 break;
1723
1724 case ACCEPT_MAC_ADDR:
1725 /* Set accepts frame bit at unicast DA filter table entry */
1726 unicast_reg =
1727 MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1728 (eth_port_num)
1729 + tbl_offset));
1730
1731 unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
1732
1733 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1734 (eth_port_num)
1735 + tbl_offset), unicast_reg);
1736
1737 break;
1738
1739 default:
1740 return false;
1741 }
1742 return true;
1743 }
1744
1745 #if 0 /* FIXME */
1746 /*******************************************************************************
1747 * eth_port_mc_addr - Multicast address settings.
1748 *
1749 * DESCRIPTION:
1750 * This API controls the MV device MAC multicast support.
1751 * The MV device supports multicast using two tables:
1752 * 1) Special Multicast Table for MAC addresses of the form
1753 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
1754 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1755 * Table entries in the DA-Filter table.
1756 * In this case, the function calls eth_port_smc_addr() routine to set the
1757 * Special Multicast Table.
1758 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1759 * is used as an index to the Other Multicast Table entries in the
1760 * DA-Filter table.
1761 * In this case, the function calculates the CRC-8bit value and calls
1762 * eth_port_omc_addr() routine to set the Other Multicast Table.
1763 * INPUT:
1764 * ETH_PORT eth_port_num Port number.
1765 * unsigned char *p_addr Unicast MAC Address.
1766 * ETH_QUEUE queue Rx queue number for this MAC address.
1767 * int option 0 = Add, 1 = remove address.
1768 *
1769 * OUTPUT:
1770 * See description.
1771 *
1772 * RETURN:
1773 * true is output succeeded.
1774 * false if add_address_table_entry( ) failed.
1775 *
1776 *******************************************************************************/
1777 static void eth_port_mc_addr (ETH_PORT eth_port_num,
1778 unsigned char *p_addr,
1779 ETH_QUEUE queue, int option)
1780 {
1781 unsigned int mac_h;
1782 unsigned int mac_l;
1783 unsigned char crc_result = 0;
1784 int mac_array[48];
1785 int crc[8];
1786 int i;
1787
1788
1789 if ((p_addr[0] == 0x01) &&
1790 (p_addr[1] == 0x00) &&
1791 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
1792
1793 eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
1794 else {
1795 /* Calculate CRC-8 out of the given address */
1796 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1797 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1798 (p_addr[4] << 8) | (p_addr[5] << 0);
1799
1800 for (i = 0; i < 32; i++)
1801 mac_array[i] = (mac_l >> i) & 0x1;
1802 for (i = 32; i < 48; i++)
1803 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1804
1805
1806 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
1807 mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
1808 mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
1809 mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1810 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1811 mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
1812 mac_array[6] ^ mac_array[0];
1813
1814 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
1815 mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
1816 mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
1817 mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1818 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
1819 mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
1820 mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
1821 mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1822 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
1823 mac_array[0];
1824
1825 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
1826 mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
1827 mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
1828 mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1829 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
1830 mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
1831 mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
1832 mac_array[2] ^ mac_array[1] ^ mac_array[0];
1833
1834 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
1835 mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
1836 mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
1837 mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1838 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
1839 mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
1840 mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
1841 mac_array[2] ^ mac_array[1];
1842
1843 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
1844 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
1845 mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
1846 mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1847 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
1848 mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
1849 mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
1850 mac_array[2];
1851
1852 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
1853 mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
1854 mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
1855 mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1856 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
1857 mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
1858 mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
1859 mac_array[3];
1860
1861 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
1862 mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
1863 mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
1864 mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
1865 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
1866 mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
1867 mac_array[6] ^ mac_array[5] ^ mac_array[4];
1868
1869 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
1870 mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
1871 mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
1872 mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
1873 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
1874 mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
1875 mac_array[6] ^ mac_array[5];
1876
1877 for (i = 0; i < 8; i++)
1878 crc_result = crc_result | (crc[i] << i);
1879
1880 eth_port_omc_addr (eth_port_num, crc_result, queue, option);
1881 }
1882 return;
1883 }
1884
1885 /*******************************************************************************
1886 * eth_port_smc_addr - Special Multicast address settings.
1887 *
1888 * DESCRIPTION:
1889 * This routine controls the MV device special MAC multicast support.
1890 * The Special Multicast Table for MAC addresses supports MAC of the form
1891 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
1892 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1893 * Table entries in the DA-Filter table.
1894 * This function set the Special Multicast Table appropriate entry
1895 * according to the argument given.
1896 *
1897 * INPUT:
1898 * ETH_PORT eth_port_num Port number.
1899 * unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
1900 * ETH_QUEUE queue Rx queue number for this MAC address.
1901 * int option 0 = Add, 1 = remove address.
1902 *
1903 * OUTPUT:
1904 * See description.
1905 *
1906 * RETURN:
1907 * true is output succeeded.
1908 * false if option parameter is invalid.
1909 *
1910 *******************************************************************************/
1911 static bool eth_port_smc_addr (ETH_PORT eth_port_num,
1912 unsigned char mc_byte,
1913 ETH_QUEUE queue, int option)
1914 {
1915 unsigned int smc_table_reg;
1916 unsigned int tbl_offset;
1917 unsigned int reg_offset;
1918
1919 /* Locate the SMC table entry */
1920 tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
1921 reg_offset = mc_byte % 4; /* Entry offset within the above register */
1922 queue &= 0x7;
1923
1924 switch (option) {
1925 case REJECT_MAC_ADDR:
1926 /* Clear accepts frame bit at specified Special DA table entry */
1927 smc_table_reg =
1928 MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1929 smc_table_reg &= (0x0E << (8 * reg_offset));
1930
1931 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
1932 break;
1933
1934 case ACCEPT_MAC_ADDR:
1935 /* Set accepts frame bit at specified Special DA table entry */
1936 smc_table_reg =
1937 MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1938 smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
1939
1940 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
1941 break;
1942
1943 default:
1944 return false;
1945 }
1946 return true;
1947 }
1948
1949 /*******************************************************************************
1950 * eth_port_omc_addr - Multicast address settings.
1951 *
1952 * DESCRIPTION:
1953 * This routine controls the MV device Other MAC multicast support.
1954 * The Other Multicast Table is used for multicast of another type.
1955 * A CRC-8bit is used as an index to the Other Multicast Table entries
1956 * in the DA-Filter table.
1957 * The function gets the CRC-8bit value from the calling routine and
1958 * set the Other Multicast Table appropriate entry according to the
1959 * CRC-8 argument given.
1960 *
1961 * INPUT:
1962 * ETH_PORT eth_port_num Port number.
1963 * unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
1964 * ETH_QUEUE queue Rx queue number for this MAC address.
1965 * int option 0 = Add, 1 = remove address.
1966 *
1967 * OUTPUT:
1968 * See description.
1969 *
1970 * RETURN:
1971 * true is output succeeded.
1972 * false if option parameter is invalid.
1973 *
1974 *******************************************************************************/
1975 static bool eth_port_omc_addr (ETH_PORT eth_port_num,
1976 unsigned char crc8,
1977 ETH_QUEUE queue, int option)
1978 {
1979 unsigned int omc_table_reg;
1980 unsigned int tbl_offset;
1981 unsigned int reg_offset;
1982
1983 /* Locate the OMC table entry */
1984 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1985 reg_offset = crc8 % 4; /* Entry offset within the above register */
1986 queue &= 0x7;
1987
1988 switch (option) {
1989 case REJECT_MAC_ADDR:
1990 /* Clear accepts frame bit at specified Other DA table entry */
1991 omc_table_reg =
1992 MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1993 omc_table_reg &= (0x0E << (8 * reg_offset));
1994
1995 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
1996 break;
1997
1998 case ACCEPT_MAC_ADDR:
1999 /* Set accepts frame bit at specified Other DA table entry */
2000 omc_table_reg =
2001 MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
2002 omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
2003
2004 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
2005 break;
2006
2007 default:
2008 return false;
2009 }
2010 return true;
2011 }
2012 #endif
2013
2014 /*******************************************************************************
2015 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2016 *
2017 * DESCRIPTION:
2018 * Go through all the DA filter tables (Unicast, Special Multicast & Other
2019 * Multicast) and set each entry to 0.
2020 *
2021 * INPUT:
2022 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2023 *
2024 * OUTPUT:
2025 * Multicast and Unicast packets are rejected.
2026 *
2027 * RETURN:
2028 * None.
2029 *
2030 *******************************************************************************/
2031 static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
2032 {
2033 int table_index;
2034
2035 /* Clear DA filter unicast table (Ex_dFUT) */
2036 for (table_index = 0; table_index <= 0xC; table_index += 4)
2037 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
2038 (eth_port_num) + table_index), 0);
2039
2040 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2041 /* Clear DA filter special multicast table (Ex_dFSMT) */
2042 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
2043 /* Clear DA filter other multicast table (Ex_dFOMT) */
2044 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
2045 }
2046 }
2047
2048 /*******************************************************************************
2049 * eth_clear_mib_counters - Clear all MIB counters
2050 *
2051 * DESCRIPTION:
2052 * This function clears all MIB counters of a specific ethernet port.
2053 * A read from the MIB counter will reset the counter.
2054 *
2055 * INPUT:
2056 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2057 *
2058 * OUTPUT:
2059 * After reading all MIB counters, the counters resets.
2060 *
2061 * RETURN:
2062 * MIB counter value.
2063 *
2064 *******************************************************************************/
2065 static void eth_clear_mib_counters (ETH_PORT eth_port_num)
2066 {
2067 int i;
2068 unsigned int dummy;
2069
2070 /* Perform dummy reads from MIB counters */
2071 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2072 i += 4)
2073 dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE
2074 (eth_port_num) + i));
2075
2076 return;
2077 }
2078
2079 /*******************************************************************************
2080 * eth_read_mib_counter - Read a MIB counter
2081 *
2082 * DESCRIPTION:
2083 * This function reads a MIB counter of a specific ethernet port.
2084 * NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
2085 * following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
2086 * register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
2087 * ETH_MIB_GOOD_OCTETS_SENT_HIGH
2088 *
2089 * INPUT:
2090 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2091 * unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros).
2092 *
2093 * OUTPUT:
2094 * After reading the MIB counter, the counter resets.
2095 *
2096 * RETURN:
2097 * MIB counter value.
2098 *
2099 *******************************************************************************/
2100 unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
2101 unsigned int mib_offset)
2102 {
2103 return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num)
2104 + mib_offset));
2105 }
2106
2107 /*******************************************************************************
2108 * ethernet_phy_set - Set the ethernet port PHY address.
2109 *
2110 * DESCRIPTION:
2111 * This routine set the ethernet port PHY address according to given
2112 * parameter.
2113 *
2114 * INPUT:
2115 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2116 *
2117 * OUTPUT:
2118 * Set PHY Address Register with given PHY address parameter.
2119 *
2120 * RETURN:
2121 * None.
2122 *
2123 *******************************************************************************/
2124 static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
2125 {
2126 unsigned int reg_data;
2127
2128 reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
2129
2130 reg_data &= ~(0x1F << (5 * eth_port_num));
2131 reg_data |= (phy_addr << (5 * eth_port_num));
2132
2133 MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data);
2134
2135 return;
2136 }
2137
2138 /*******************************************************************************
2139 * ethernet_phy_get - Get the ethernet port PHY address.
2140 *
2141 * DESCRIPTION:
2142 * This routine returns the given ethernet port PHY address.
2143 *
2144 * INPUT:
2145 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2146 *
2147 * OUTPUT:
2148 * None.
2149 *
2150 * RETURN:
2151 * PHY address.
2152 *
2153 *******************************************************************************/
2154 static int ethernet_phy_get (ETH_PORT eth_port_num)
2155 {
2156 unsigned int reg_data;
2157
2158 reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
2159
2160 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2161 }
2162
2163 /*******************************************************************************
2164 * ethernet_phy_reset - Reset Ethernet port PHY.
2165 *
2166 * DESCRIPTION:
2167 * This routine utilize the SMI interface to reset the ethernet port PHY.
2168 * The routine waits until the link is up again or link up is timeout.
2169 *
2170 * INPUT:
2171 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2172 *
2173 * OUTPUT:
2174 * The ethernet port PHY renew its link.
2175 *
2176 * RETURN:
2177 * None.
2178 *
2179 *******************************************************************************/
2180 static bool ethernet_phy_reset (ETH_PORT eth_port_num)
2181 {
2182 unsigned int time_out = 50;
2183 unsigned int phy_reg_data;
2184
2185 /* Reset the PHY */
2186 eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
2187 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2188 eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
2189
2190 /* Poll on the PHY LINK */
2191 do {
2192 eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
2193
2194 if (time_out-- == 0)
2195 return false;
2196 }
2197 while (!(phy_reg_data & 0x20));
2198
2199 return true;
2200 }
2201
2202 /*******************************************************************************
2203 * eth_port_reset - Reset Ethernet port
2204 *
2205 * DESCRIPTION:
2206 * This routine resets the chip by aborting any SDMA engine activity and
2207 * clearing the MIB counters. The Receiver and the Transmit unit are in
2208 * idle state after this command is performed and the port is disabled.
2209 *
2210 * INPUT:
2211 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2212 *
2213 * OUTPUT:
2214 * Channel activity is halted.
2215 *
2216 * RETURN:
2217 * None.
2218 *
2219 *******************************************************************************/
2220 static void eth_port_reset (ETH_PORT eth_port_num)
2221 {
2222 unsigned int reg_data;
2223
2224 /* Stop Tx port activity. Check port Tx activity. */
2225 reg_data =
2226 MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
2227 (eth_port_num));
2228
2229 if (reg_data & 0xFF) {
2230 /* Issue stop command for active channels only */
2231 MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
2232 (eth_port_num), (reg_data << 8));
2233
2234 /* Wait for all Tx activity to terminate. */
2235 do {
2236 /* Check port cause register that all Tx queues are stopped */
2237 reg_data =
2238 MV_REG_READ
2239 (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
2240 (eth_port_num));
2241 }
2242 while (reg_data & 0xFF);
2243 }
2244
2245 /* Stop Rx port activity. Check port Rx activity. */
2246 reg_data =
2247 MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
2248 (eth_port_num));
2249
2250 if (reg_data & 0xFF) {
2251 /* Issue stop command for active channels only */
2252 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
2253 (eth_port_num), (reg_data << 8));
2254
2255 /* Wait for all Rx activity to terminate. */
2256 do {
2257 /* Check port cause register that all Rx queues are stopped */
2258 reg_data =
2259 MV_REG_READ
2260 (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
2261 (eth_port_num));
2262 }
2263 while (reg_data & 0xFF);
2264 }
2265
2266
2267 /* Clear all MIB counters */
2268 eth_clear_mib_counters (eth_port_num);
2269
2270 /* Reset the Enable bit in the Configuration Register */
2271 reg_data =
2272 MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG
2273 (eth_port_num));
2274 reg_data &= ~ETH_SERIAL_PORT_ENABLE;
2275 MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
2276 reg_data);
2277
2278 return;
2279 }
2280
2281 #if 0 /* Not needed here */
2282 /*******************************************************************************
2283 * ethernet_set_config_reg - Set specified bits in configuration register.
2284 *
2285 * DESCRIPTION:
2286 * This function sets specified bits in the given ethernet
2287 * configuration register.
2288 *
2289 * INPUT:
2290 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2291 * unsigned int value 32 bit value.
2292 *
2293 * OUTPUT:
2294 * The set bits in the value parameter are set in the configuration
2295 * register.
2296 *
2297 * RETURN:
2298 * None.
2299 *
2300 *******************************************************************************/
2301 static void ethernet_set_config_reg (ETH_PORT eth_port_num,
2302 unsigned int value)
2303 {
2304 unsigned int eth_config_reg;
2305
2306 eth_config_reg =
2307 MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num));
2308 eth_config_reg |= value;
2309 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
2310 eth_config_reg);
2311
2312 return;
2313 }
2314 #endif
2315
2316 #if 0 /* FIXME */
2317 /*******************************************************************************
2318 * ethernet_reset_config_reg - Reset specified bits in configuration register.
2319 *
2320 * DESCRIPTION:
2321 * This function resets specified bits in the given Ethernet
2322 * configuration register.
2323 *
2324 * INPUT:
2325 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2326 * unsigned int value 32 bit value.
2327 *
2328 * OUTPUT:
2329 * The set bits in the value parameter are reset in the configuration
2330 * register.
2331 *
2332 * RETURN:
2333 * None.
2334 *
2335 *******************************************************************************/
2336 static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
2337 unsigned int value)
2338 {
2339 unsigned int eth_config_reg;
2340
2341 eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
2342 (eth_port_num));
2343 eth_config_reg &= ~value;
2344 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
2345 eth_config_reg);
2346
2347 return;
2348 }
2349 #endif
2350
2351 #if 0 /* Not needed here */
2352 /*******************************************************************************
2353 * ethernet_get_config_reg - Get the port configuration register
2354 *
2355 * DESCRIPTION:
2356 * This function returns the configuration register value of the given
2357 * ethernet port.
2358 *
2359 * INPUT:
2360 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2361 *
2362 * OUTPUT:
2363 * None.
2364 *
2365 * RETURN:
2366 * Port configuration register value.
2367 *
2368 *******************************************************************************/
2369 static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
2370 {
2371 unsigned int eth_config_reg;
2372
2373 eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
2374 (eth_port_num));
2375 return eth_config_reg;
2376 }
2377
2378 #endif
2379
2380 /*******************************************************************************
2381 * eth_port_read_smi_reg - Read PHY registers
2382 *
2383 * DESCRIPTION:
2384 * This routine utilize the SMI interface to interact with the PHY in
2385 * order to perform PHY register read.
2386 *
2387 * INPUT:
2388 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2389 * unsigned int phy_reg PHY register address offset.
2390 * unsigned int *value Register value buffer.
2391 *
2392 * OUTPUT:
2393 * Write the value of a specified PHY register into given buffer.
2394 *
2395 * RETURN:
2396 * false if the PHY is busy or read data is not in valid state.
2397 * true otherwise.
2398 *
2399 *******************************************************************************/
2400 static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
2401 unsigned int phy_reg, unsigned int *value)
2402 {
2403 unsigned int reg_value;
2404 unsigned int time_out = PHY_BUSY_TIMEOUT;
2405 int phy_addr;
2406
2407 phy_addr = ethernet_phy_get (eth_port_num);
2408 /* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/
2409
2410 /* first check that it is not busy */
2411 do {
2412 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2413 if (time_out-- == 0) {
2414 return false;
2415 }
2416 }
2417 while (reg_value & ETH_SMI_BUSY);
2418
2419 /* not busy */
2420
2421 MV_REG_WRITE (MV64360_ETH_SMI_REG,
2422 (phy_addr << 16) | (phy_reg << 21) |
2423 ETH_SMI_OPCODE_READ);
2424
2425 time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
2426
2427 do {
2428 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2429 if (time_out-- == 0) {
2430 return false;
2431 }
2432 }
2433 while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
2434
2435 /* Wait for the data to update in the SMI register */
2436 #define PHY_UPDATE_TIMEOUT 10000
2437 for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
2438
2439 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2440
2441 *value = reg_value & 0xffff;
2442
2443 return true;
2444 }
2445
2446 /*******************************************************************************
2447 * eth_port_write_smi_reg - Write to PHY registers
2448 *
2449 * DESCRIPTION:
2450 * This routine utilize the SMI interface to interact with the PHY in
2451 * order to perform writes to PHY registers.
2452 *
2453 * INPUT:
2454 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2455 * unsigned int phy_reg PHY register address offset.
2456 * unsigned int value Register value.
2457 *
2458 * OUTPUT:
2459 * Write the given value to the specified PHY register.
2460 *
2461 * RETURN:
2462 * false if the PHY is busy.
2463 * true otherwise.
2464 *
2465 *******************************************************************************/
2466 static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
2467 unsigned int phy_reg, unsigned int value)
2468 {
2469 unsigned int reg_value;
2470 unsigned int time_out = PHY_BUSY_TIMEOUT;
2471 int phy_addr;
2472
2473 phy_addr = ethernet_phy_get (eth_port_num);
2474
2475 /* first check that it is not busy */
2476 do {
2477 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2478 if (time_out-- == 0) {
2479 return false;
2480 }
2481 }
2482 while (reg_value & ETH_SMI_BUSY);
2483
2484 /* not busy */
2485 MV_REG_WRITE (MV64360_ETH_SMI_REG,
2486 (phy_addr << 16) | (phy_reg << 21) |
2487 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2488 return true;
2489 }
2490
2491 /*******************************************************************************
2492 * eth_set_access_control - Config address decode parameters for Ethernet unit
2493 *
2494 * DESCRIPTION:
2495 * This function configures the address decode parameters for the Gigabit
2496 * Ethernet Controller according the given parameters struct.
2497 *
2498 * INPUT:
2499 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2500 * ETH_WIN_PARAM *param Address decode parameter struct.
2501 *
2502 * OUTPUT:
2503 * An access window is opened using the given access parameters.
2504 *
2505 * RETURN:
2506 * None.
2507 *
2508 *******************************************************************************/
2509 static void eth_set_access_control (ETH_PORT eth_port_num,
2510 ETH_WIN_PARAM * param)
2511 {
2512 unsigned int access_prot_reg;
2513
2514 /* Set access control register */
2515 access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG
2516 (eth_port_num));
2517 access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */
2518 access_prot_reg |= (param->access_ctrl << (param->win * 2));
2519 MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num),
2520 access_prot_reg);
2521
2522 /* Set window Size reg (SR) */
2523 MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 +
2524 (ETH_SIZE_REG_GAP * param->win)),
2525 (((param->size / 0x10000) - 1) << 16));
2526
2527 /* Set window Base address reg (BA) */
2528 MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
2529 (param->target | param->attributes | param->base_addr));
2530 /* High address remap reg (HARR) */
2531 if (param->win < 4)
2532 MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 +
2533 (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
2534 param->high_addr);
2535
2536 /* Base address enable reg (BARER) */
2537 if (param->enable == 1)
2538 MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
2539 (1 << param->win));
2540 else
2541 MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
2542 (1 << param->win));
2543 }
2544
2545 /*******************************************************************************
2546 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
2547 *
2548 * DESCRIPTION:
2549 * This function prepares a Rx chained list of descriptors and packet
2550 * buffers in a form of a ring. The routine must be called after port
2551 * initialization routine and before port start routine.
2552 * The Ethernet SDMA engine uses CPU bus addresses to access the various
2553 * devices in the system (i.e. DRAM). This function uses the ethernet
2554 * struct 'virtual to physical' routine (set by the user) to set the ring
2555 * with physical addresses.
2556 *
2557 * INPUT:
2558 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2559 * ETH_QUEUE rx_queue Number of Rx queue.
2560 * int rx_desc_num Number of Rx descriptors
2561 * int rx_buff_size Size of Rx buffer
2562 * unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
2563 * unsigned int rx_buff_base_addr Rx buffer memory area base addr.
2564 *
2565 * OUTPUT:
2566 * The routine updates the Ethernet port control struct with information
2567 * regarding the Rx descriptors and buffers.
2568 *
2569 * RETURN:
2570 * false if the given descriptors memory area is not aligned according to
2571 * Ethernet SDMA specifications.
2572 * true otherwise.
2573 *
2574 *******************************************************************************/
2575 static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
2576 ETH_QUEUE rx_queue,
2577 int rx_desc_num,
2578 int rx_buff_size,
2579 unsigned int rx_desc_base_addr,
2580 unsigned int rx_buff_base_addr)
2581 {
2582 ETH_RX_DESC *p_rx_desc;
2583 ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */
2584 unsigned int buffer_addr;
2585 int ix; /* a counter */
2586
2587
2588 p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
2589 p_rx_prev_desc = p_rx_desc;
2590 buffer_addr = rx_buff_base_addr;
2591
2592 /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
2593 if (rx_buff_base_addr & 0xF)
2594 return false;
2595
2596 /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */
2597 if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
2598 return false;
2599
2600 /* Rx buffers must be 64-bit aligned. */
2601 if ((rx_buff_base_addr + rx_buff_size) & 0x7)
2602 return false;
2603
2604 /* initialize the Rx descriptors ring */
2605 for (ix = 0; ix < rx_desc_num; ix++) {
2606 p_rx_desc->buf_size = rx_buff_size;
2607 p_rx_desc->byte_cnt = 0x0000;
2608 p_rx_desc->cmd_sts =
2609 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2610 p_rx_desc->next_desc_ptr =
2611 ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
2612 p_rx_desc->buf_ptr = buffer_addr;
2613 p_rx_desc->return_info = 0x00000000;
2614 D_CACHE_FLUSH_LINE (p_rx_desc, 0);
2615 buffer_addr += rx_buff_size;
2616 p_rx_prev_desc = p_rx_desc;
2617 p_rx_desc = (ETH_RX_DESC *)
2618 ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
2619 }
2620
2621 /* Closing Rx descriptors ring */
2622 p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
2623 D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
2624
2625 /* Save Rx desc pointer to driver struct. */
2626 CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
2627 USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
2628
2629 p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
2630 (ETH_RX_DESC *) rx_desc_base_addr;
2631 p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
2632 rx_desc_num * RX_DESC_ALIGNED_SIZE;
2633
2634 p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
2635
2636 return true;
2637 }
2638
2639 /*******************************************************************************
2640 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
2641 *
2642 * DESCRIPTION:
2643 * This function prepares a Tx chained list of descriptors and packet
2644 * buffers in a form of a ring. The routine must be called after port
2645 * initialization routine and before port start routine.
2646 * The Ethernet SDMA engine uses CPU bus addresses to access the various
2647 * devices in the system (i.e. DRAM). This function uses the ethernet
2648 * struct 'virtual to physical' routine (set by the user) to set the ring
2649 * with physical addresses.
2650 *
2651 * INPUT:
2652 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2653 * ETH_QUEUE tx_queue Number of Tx queue.
2654 * int tx_desc_num Number of Tx descriptors
2655 * int tx_buff_size Size of Tx buffer
2656 * unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
2657 * unsigned int tx_buff_base_addr Tx buffer memory area base addr.
2658 *
2659 * OUTPUT:
2660 * The routine updates the Ethernet port control struct with information
2661 * regarding the Tx descriptors and buffers.
2662 *
2663 * RETURN:
2664 * false if the given descriptors memory area is not aligned according to
2665 * Ethernet SDMA specifications.
2666 * true otherwise.
2667 *
2668 *******************************************************************************/
2669 static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
2670 ETH_QUEUE tx_queue,
2671 int tx_desc_num,
2672 int tx_buff_size,
2673 unsigned int tx_desc_base_addr,
2674 unsigned int tx_buff_base_addr)
2675 {
2676
2677 ETH_TX_DESC *p_tx_desc;
2678 ETH_TX_DESC *p_tx_prev_desc;
2679 unsigned int buffer_addr;
2680 int ix; /* a counter */
2681
2682
2683 /* save the first desc pointer to link with the last descriptor */
2684 p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
2685 p_tx_prev_desc = p_tx_desc;
2686 buffer_addr = tx_buff_base_addr;
2687
2688 /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
2689 if (tx_buff_base_addr & 0xF)
2690 return false;
2691
2692 /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */
2693 if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
2694 || (tx_buff_size < TX_BUFFER_MIN_SIZE))
2695 return false;
2696
2697 /* Initialize the Tx descriptors ring */
2698 for (ix = 0; ix < tx_desc_num; ix++) {
2699 p_tx_desc->byte_cnt = 0x0000;
2700 p_tx_desc->l4i_chk = 0x0000;
2701 p_tx_desc->cmd_sts = 0x00000000;
2702 p_tx_desc->next_desc_ptr =
2703 ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
2704
2705 p_tx_desc->buf_ptr = buffer_addr;
2706 p_tx_desc->return_info = 0x00000000;
2707 D_CACHE_FLUSH_LINE (p_tx_desc, 0);
2708 buffer_addr += tx_buff_size;
2709 p_tx_prev_desc = p_tx_desc;
2710 p_tx_desc = (ETH_TX_DESC *)
2711 ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
2712
2713 }
2714 /* Closing Tx descriptors ring */
2715 p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
2716 D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
2717 /* Set Tx desc pointer in driver struct. */
2718 CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
2719 USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
2720
2721 /* Init Tx ring base and size parameters */
2722 p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
2723 (ETH_TX_DESC *) tx_desc_base_addr;
2724 p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
2725 (tx_desc_num * TX_DESC_ALIGNED_SIZE);
2726
2727 /* Add the queue to the list of Tx queues of this port */
2728 p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
2729
2730 return true;
2731 }
2732
2733 /*******************************************************************************
2734 * eth_port_send - Send an Ethernet packet
2735 *
2736 * DESCRIPTION:
2737 * This routine send a given packet described by p_pktinfo parameter. It
2738 * supports transmitting of a packet spaned over multiple buffers. The
2739 * routine updates 'curr' and 'first' indexes according to the packet
2740 * segment passed to the routine. In case the packet segment is first,
2741 * the 'first' index is update. In any case, the 'curr' index is updated.
2742 * If the routine get into Tx resource error it assigns 'curr' index as
2743 * 'first'. This way the function can abort Tx process of multiple
2744 * descriptors per packet.
2745 *
2746 * INPUT:
2747 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2748 * ETH_QUEUE tx_queue Number of Tx queue.
2749 * PKT_INFO *p_pkt_info User packet buffer.
2750 *
2751 * OUTPUT:
2752 * Tx ring 'curr' and 'first' indexes are updated.
2753 *
2754 * RETURN:
2755 * ETH_QUEUE_FULL in case of Tx resource error.
2756 * ETH_ERROR in case the routine can not access Tx desc ring.
2757 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2758 * ETH_OK otherwise.
2759 *
2760 *******************************************************************************/
2761 static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
2762 ETH_QUEUE tx_queue,
2763 PKT_INFO * p_pkt_info)
2764 {
2765 volatile ETH_TX_DESC *p_tx_desc_first;
2766 volatile ETH_TX_DESC *p_tx_desc_curr;
2767 volatile ETH_TX_DESC *p_tx_next_desc_curr;
2768 volatile ETH_TX_DESC *p_tx_desc_used;
2769 unsigned int command_status;
2770
2771 /* Do not process Tx ring in case of Tx ring resource error */
2772 if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
2773 return ETH_QUEUE_FULL;
2774
2775 /* Get the Tx Desc ring indexes */
2776 CURR_TFD_GET (p_tx_desc_curr, tx_queue);
2777 USED_TFD_GET (p_tx_desc_used, tx_queue);
2778
2779 if (p_tx_desc_curr == NULL)
2780 return ETH_ERROR;
2781
2782 /* The following parameters are used to save readings from memory */
2783 p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
2784 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2785
2786 if (command_status & (ETH_TX_FIRST_DESC)) {
2787 /* Update first desc */
2788 FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
2789 p_tx_desc_first = p_tx_desc_curr;
2790 } else {
2791 FIRST_TFD_GET (p_tx_desc_first, tx_queue);
2792 command_status |= ETH_BUFFER_OWNED_BY_DMA;
2793 }
2794
2795 /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
2796 /* boundary. We use the memory allocated for Tx descriptor. This memory */
2797 /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
2798 if (p_pkt_info->byte_cnt <= 8) {
2799 printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */
2800 return ETH_ERROR;
2801
2802 p_tx_desc_curr->buf_ptr =
2803 (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
2804 eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
2805 p_pkt_info->byte_cnt);
2806 } else
2807 p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
2808
2809 p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
2810 p_tx_desc_curr->return_info = p_pkt_info->return_info;
2811
2812 if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
2813 /* Set last desc with DMA ownership and interrupt enable. */
2814 p_tx_desc_curr->cmd_sts = command_status |
2815 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2816
2817 if (p_tx_desc_curr != p_tx_desc_first)
2818 p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
2819
2820 /* Flush CPU pipe */
2821
2822 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
2823 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
2824 CPU_PIPE_FLUSH;
2825
2826 /* Apply send command */
2827 ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
2828
2829 /* Finish Tx packet. Update first desc in case of Tx resource error */
2830 p_tx_desc_first = p_tx_next_desc_curr;
2831 FIRST_TFD_SET (p_tx_desc_first, tx_queue);
2832
2833 } else {
2834 p_tx_desc_curr->cmd_sts = command_status;
2835 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
2836 }
2837
2838 /* Check for ring index overlap in the Tx desc ring */
2839 if (p_tx_next_desc_curr == p_tx_desc_used) {
2840 /* Update the current descriptor */
2841 CURR_TFD_SET (p_tx_desc_first, tx_queue);
2842
2843 p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
2844 return ETH_QUEUE_LAST_RESOURCE;
2845 } else {
2846 /* Update the current descriptor */
2847 CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
2848 return ETH_OK;
2849 }
2850 }
2851
2852 /*******************************************************************************
2853 * eth_tx_return_desc - Free all used Tx descriptors
2854 *
2855 * DESCRIPTION:
2856 * This routine returns the transmitted packet information to the caller.
2857 * It uses the 'first' index to support Tx desc return in case a transmit
2858 * of a packet spanned over multiple buffer still in process.
2859 * In case the Tx queue was in "resource error" condition, where there are
2860 * no available Tx resources, the function resets the resource error flag.
2861 *
2862 * INPUT:
2863 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2864 * ETH_QUEUE tx_queue Number of Tx queue.
2865 * PKT_INFO *p_pkt_info User packet buffer.
2866 *
2867 * OUTPUT:
2868 * Tx ring 'first' and 'used' indexes are updated.
2869 *
2870 * RETURN:
2871 * ETH_ERROR in case the routine can not access Tx desc ring.
2872 * ETH_RETRY in case there is transmission in process.
2873 * ETH_END_OF_JOB if the routine has nothing to release.
2874 * ETH_OK otherwise.
2875 *
2876 *******************************************************************************/
2877 static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
2878 p_eth_port_ctrl,
2879 ETH_QUEUE tx_queue,
2880 PKT_INFO * p_pkt_info)
2881 {
2882 volatile ETH_TX_DESC *p_tx_desc_used = NULL;
2883 volatile ETH_TX_DESC *p_tx_desc_first = NULL;
2884 unsigned int command_status;
2885
2886
2887 /* Get the Tx Desc ring indexes */
2888 USED_TFD_GET (p_tx_desc_used, tx_queue);
2889 FIRST_TFD_GET (p_tx_desc_first, tx_queue);
2890
2891
2892 /* Sanity check */
2893 if (p_tx_desc_used == NULL)
2894 return ETH_ERROR;
2895
2896 command_status = p_tx_desc_used->cmd_sts;
2897
2898 /* Still transmitting... */
2899 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2900 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2901 return ETH_RETRY;
2902 }
2903
2904 /* Stop release. About to overlap the current available Tx descriptor */
2905 if ((p_tx_desc_used == p_tx_desc_first) &&
2906 (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
2907 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2908 return ETH_END_OF_JOB;
2909 }
2910
2911 /* Pass the packet information to the caller */
2912 p_pkt_info->cmd_sts = command_status;
2913 p_pkt_info->return_info = p_tx_desc_used->return_info;
2914 p_tx_desc_used->return_info = 0;
2915
2916 /* Update the next descriptor to release. */
2917 USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
2918
2919 /* Any Tx return cancels the Tx resource error status */
2920 if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
2921 p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
2922
2923 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2924
2925 return ETH_OK;
2926
2927 }
2928
2929 /*******************************************************************************
2930 * eth_port_receive - Get received information from Rx ring.
2931 *
2932 * DESCRIPTION:
2933 * This routine returns the received data to the caller. There is no
2934 * data copying during routine operation. All information is returned
2935 * using pointer to packet information struct passed from the caller.
2936 * If the routine exhausts Rx ring resources then the resource error flag
2937 * is set.
2938 *
2939 * INPUT:
2940 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2941 * ETH_QUEUE rx_queue Number of Rx queue.
2942 * PKT_INFO *p_pkt_info User packet buffer.
2943 *
2944 * OUTPUT:
2945 * Rx ring current and used indexes are updated.
2946 *
2947 * RETURN:
2948 * ETH_ERROR in case the routine can not access Rx desc ring.
2949 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2950 * ETH_END_OF_JOB if there is no received data.
2951 * ETH_OK otherwise.
2952 *
2953 *******************************************************************************/
2954 static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
2955 ETH_QUEUE rx_queue,
2956 PKT_INFO * p_pkt_info)
2957 {
2958 volatile ETH_RX_DESC *p_rx_curr_desc;
2959 volatile ETH_RX_DESC *p_rx_next_curr_desc;
2960 volatile ETH_RX_DESC *p_rx_used_desc;
2961 unsigned int command_status;
2962
2963 /* Do not process Rx ring in case of Rx ring resource error */
2964 if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
2965 printf ("\nRx Queue is full ...\n");
2966 return ETH_QUEUE_FULL;
2967 }
2968
2969 /* Get the Rx Desc ring 'curr and 'used' indexes */
2970 CURR_RFD_GET (p_rx_curr_desc, rx_queue);
2971 USED_RFD_GET (p_rx_used_desc, rx_queue);
2972
2973 /* Sanity check */
2974 if (p_rx_curr_desc == NULL)
2975 return ETH_ERROR;
2976
2977 /* The following parameters are used to save readings from memory */
2978 p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
2979 command_status = p_rx_curr_desc->cmd_sts;
2980
2981 /* Nothing to receive... */
2982 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2983 /* DP(printf("Rx: command_status: %08x\n", command_status)); */
2984 D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
2985 /* DP(printf("\nETH_END_OF_JOB ...\n"));*/
2986 return ETH_END_OF_JOB;
2987 }
2988
2989 p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
2990 p_pkt_info->cmd_sts = command_status;
2991 p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
2992 p_pkt_info->return_info = p_rx_curr_desc->return_info;
2993 p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
2994
2995 /* Clean the return info field to indicate that the packet has been */
2996 /* moved to the upper layers */
2997 p_rx_curr_desc->return_info = 0;
2998
2999 /* Update 'curr' in data structure */
3000 CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
3001
3002 /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
3003 if (p_rx_next_curr_desc == p_rx_used_desc)
3004 p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
3005
3006 D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
3007 CPU_PIPE_FLUSH;
3008 return ETH_OK;
3009 }
3010
3011 /*******************************************************************************
3012 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
3013 *
3014 * DESCRIPTION:
3015 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
3016 * next 'used' descriptor and attached the returned buffer to it.
3017 * In case the Rx ring was in "resource error" condition, where there are
3018 * no available Rx resources, the function resets the resource error flag.
3019 *
3020 * INPUT:
3021 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
3022 * ETH_QUEUE rx_queue Number of Rx queue.
3023 * PKT_INFO *p_pkt_info Information on the returned buffer.
3024 *
3025 * OUTPUT:
3026 * New available Rx resource in Rx descriptor ring.
3027 *
3028 * RETURN:
3029 * ETH_ERROR in case the routine can not access Rx desc ring.
3030 * ETH_OK otherwise.
3031 *
3032 *******************************************************************************/
3033 static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
3034 p_eth_port_ctrl,
3035 ETH_QUEUE rx_queue,
3036 PKT_INFO * p_pkt_info)
3037 {
3038 volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */
3039
3040 /* Get 'used' Rx descriptor */
3041 USED_RFD_GET (p_used_rx_desc, rx_queue);
3042
3043 /* Sanity check */
3044 if (p_used_rx_desc == NULL)
3045 return ETH_ERROR;
3046
3047 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
3048 p_used_rx_desc->return_info = p_pkt_info->return_info;
3049 p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
3050 p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */
3051
3052 /* Flush the write pipe */
3053 CPU_PIPE_FLUSH;
3054
3055 /* Return the descriptor to DMA ownership */
3056 p_used_rx_desc->cmd_sts =
3057 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
3058
3059 /* Flush descriptor and CPU pipe */
3060 D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
3061 CPU_PIPE_FLUSH;
3062
3063 /* Move the used descriptor pointer to the next descriptor */
3064 USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
3065
3066 /* Any Rx return cancels the Rx resource error status */
3067 if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
3068 p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
3069
3070 return ETH_OK;
3071 }
3072
3073 /*******************************************************************************
3074 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
3075 *
3076 * DESCRIPTION:
3077 * This routine sets the RX coalescing interrupt mechanism parameter.
3078 * This parameter is a timeout counter, that counts in 64 t_clk
3079 * chunks ; that when timeout event occurs a maskable interrupt
3080 * occurs.
3081 * The parameter is calculated using the tClk of the MV-643xx chip
3082 * , and the required delay of the interrupt in usec.
3083 *
3084 * INPUT:
3085 * ETH_PORT eth_port_num Ethernet port number
3086 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
3087 * unsigned int delay Delay in usec
3088 *
3089 * OUTPUT:
3090 * Interrupt coalescing mechanism value is set in MV-643xx chip.
3091 *
3092 * RETURN:
3093 * The interrupt coalescing value set in the gigE port.
3094 *
3095 *******************************************************************************/
3096 #if 0 /* FIXME */
3097 static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
3098 unsigned int t_clk,
3099 unsigned int delay)
3100 {
3101 unsigned int coal;
3102
3103 coal = ((t_clk / 1000000) * delay) / 64;
3104 /* Set RX Coalescing mechanism */
3105 MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
3106 ((coal & 0x3fff) << 8) |
3107 (MV_REG_READ
3108 (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num))
3109 & 0xffc000ff));
3110 return coal;
3111 }
3112
3113 #endif
3114 /*******************************************************************************
3115 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
3116 *
3117 * DESCRIPTION:
3118 * This routine sets the TX coalescing interrupt mechanism parameter.
3119 * This parameter is a timeout counter, that counts in 64 t_clk
3120 * chunks ; that when timeout event occurs a maskable interrupt
3121 * occurs.
3122 * The parameter is calculated using the t_cLK frequency of the
3123 * MV-643xx chip and the required delay in the interrupt in uSec
3124 *
3125 * INPUT:
3126 * ETH_PORT eth_port_num Ethernet port number
3127 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
3128 * unsigned int delay Delay in uSeconds
3129 *
3130 * OUTPUT:
3131 * Interrupt coalescing mechanism value is set in MV-643xx chip.
3132 *
3133 * RETURN:
3134 * The interrupt coalescing value set in the gigE port.
3135 *
3136 *******************************************************************************/
3137 #if 0 /* FIXME */
3138 static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
3139 unsigned int t_clk,
3140 unsigned int delay)
3141 {
3142 unsigned int coal;
3143
3144 coal = ((t_clk / 1000000) * delay) / 64;
3145 /* Set TX Coalescing mechanism */
3146 MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
3147 coal << 4);
3148 return coal;
3149 }
3150 #endif
3151
3152 /*******************************************************************************
3153 * eth_b_copy - Copy bytes from source to destination
3154 *
3155 * DESCRIPTION:
3156 * This function supports the eight bytes limitation on Tx buffer size.
3157 * The routine will zero eight bytes starting from the destination address
3158 * followed by copying bytes from the source address to the destination.
3159 *
3160 * INPUT:
3161 * unsigned int src_addr 32 bit source address.
3162 * unsigned int dst_addr 32 bit destination address.
3163 * int byte_count Number of bytes to copy.
3164 *
3165 * OUTPUT:
3166 * See description.
3167 *
3168 * RETURN:
3169 * None.
3170 *
3171 *******************************************************************************/
3172 static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
3173 int byte_count)
3174 {
3175 /* Zero the dst_addr area */
3176 *(unsigned int *) dst_addr = 0x0;
3177
3178 while (byte_count != 0) {
3179 *(char *) dst_addr = *(char *) src_addr;
3180 dst_addr++;
3181 src_addr++;
3182 byte_count--;
3183 }
3184 }
"Das U-Boot" Source Tree