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rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / board / esd / du440 / du440.c
1 /*
2 * (C) Copyright 2008
3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21 #include <common.h>
22 #include <asm/processor.h>
23 #include <asm/io.h>
24 #include <asm/bitops.h>
25 #include <command.h>
26 #include <i2c.h>
27 #include <ppc440.h>
28 #include "du440.h"
29
30 DECLARE_GLOBAL_DATA_PTR;
31
32 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
33 extern ulong flash_get_size (ulong base, int banknum);
34
35 int usbhub_init(void);
36 int dvi_init(void);
37 int eeprom_write_enable (unsigned dev_addr, int state);
38 int board_revision(void);
39
40 static int du440_post_errors;
41
42 int board_early_init_f(void)
43 {
44 u32 sdr0_cust0;
45 u32 sdr0_pfc1, sdr0_pfc2;
46 u32 reg;
47
48 mtdcr(ebccfga, xbcfg);
49 mtdcr(ebccfgd, 0xb8400000);
50
51 /*
52 * Setup the GPIO pins
53 */
54 out_be32((void*)GPIO0_OR, 0x00000000 | CONFIG_SYS_GPIO0_EP_EEP);
55 out_be32((void*)GPIO0_TCR, 0x0000001f | CONFIG_SYS_GPIO0_EP_EEP);
56 out_be32((void*)GPIO0_OSRL, 0x50055400);
57 out_be32((void*)GPIO0_OSRH, 0x55005000);
58 out_be32((void*)GPIO0_TSRL, 0x50055400);
59 out_be32((void*)GPIO0_TSRH, 0x55005000);
60 out_be32((void*)GPIO0_ISR1L, 0x50000000);
61 out_be32((void*)GPIO0_ISR1H, 0x00000000);
62 out_be32((void*)GPIO0_ISR2L, 0x00000000);
63 out_be32((void*)GPIO0_ISR2H, 0x00000000);
64 out_be32((void*)GPIO0_ISR3L, 0x00000000);
65 out_be32((void*)GPIO0_ISR3H, 0x00000000);
66
67 out_be32((void*)GPIO1_OR, 0x00000000);
68 out_be32((void*)GPIO1_TCR, 0xc2000000 |
69 CONFIG_SYS_GPIO1_IORSTN |
70 CONFIG_SYS_GPIO1_IORST2N |
71 CONFIG_SYS_GPIO1_LEDUSR1 |
72 CONFIG_SYS_GPIO1_LEDUSR2 |
73 CONFIG_SYS_GPIO1_LEDPOST |
74 CONFIG_SYS_GPIO1_LEDDU);
75 out_be32((void*)GPIO1_ODR, CONFIG_SYS_GPIO1_LEDDU);
76 out_be32((void*)GPIO1_OSRL, 0x0c280000);
77 out_be32((void*)GPIO1_OSRH, 0x00000000);
78 out_be32((void*)GPIO1_TSRL, 0xcc000000);
79 out_be32((void*)GPIO1_TSRH, 0x00000000);
80 out_be32((void*)GPIO1_ISR1L, 0x00005550);
81 out_be32((void*)GPIO1_ISR1H, 0x00000000);
82 out_be32((void*)GPIO1_ISR2L, 0x00050000);
83 out_be32((void*)GPIO1_ISR2H, 0x00000000);
84 out_be32((void*)GPIO1_ISR3L, 0x01400000);
85 out_be32((void*)GPIO1_ISR3H, 0x00000000);
86
87 /*
88 * Setup the interrupt controller polarities, triggers, etc.
89 */
90 mtdcr(uic0sr, 0xffffffff); /* clear all */
91 mtdcr(uic0er, 0x00000000); /* disable all */
92 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
93 mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
94 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
95 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
96 mtdcr(uic0sr, 0xffffffff); /* clear all */
97
98 /*
99 * UIC1:
100 * bit30: ext. Irq 1: PLD : int 32+30
101 */
102 mtdcr(uic1sr, 0xffffffff); /* clear all */
103 mtdcr(uic1er, 0x00000000); /* disable all */
104 mtdcr(uic1cr, 0x00000000); /* all non-critical */
105 mtdcr(uic1pr, 0xfffffffd);
106 mtdcr(uic1tr, 0x00000000);
107 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
108 mtdcr(uic1sr, 0xffffffff); /* clear all */
109
110 /*
111 * UIC2
112 * bit3: ext. Irq 2: DCF77 : int 64+3
113 */
114 mtdcr(uic2sr, 0xffffffff); /* clear all */
115 mtdcr(uic2er, 0x00000000); /* disable all */
116 mtdcr(uic2cr, 0x00000000); /* all non-critical */
117 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
118 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
119 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
120 mtdcr(uic2sr, 0xffffffff); /* clear all */
121
122 /* select Ethernet pins */
123 mfsdr(SDR0_PFC1, sdr0_pfc1);
124 mfsdr(SDR0_PFC2, sdr0_pfc2);
125
126 /* setup EMAC bridge interface */
127 if (board_revision() == 0) {
128 /* 1 x MII */
129 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
130 SDR0_PFC1_SELECT_CONFIG_1_2;
131 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
132 SDR0_PFC2_SELECT_CONFIG_1_2;
133 } else {
134 /* 2 x SMII */
135 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
136 SDR0_PFC1_SELECT_CONFIG_6;
137 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
138 SDR0_PFC2_SELECT_CONFIG_6;
139 }
140
141 /* enable 2nd IIC */
142 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
143
144 mtsdr(SDR0_PFC2, sdr0_pfc2);
145 mtsdr(SDR0_PFC1, sdr0_pfc1);
146
147 /* PCI arbiter enabled */
148 mfsdr(sdr_pci0, reg);
149 mtsdr(sdr_pci0, 0x80000000 | reg);
150
151 /* setup NAND FLASH */
152 mfsdr(SDR0_CUST0, sdr0_cust0);
153 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
154 SDR0_CUST0_NDFC_ENABLE |
155 SDR0_CUST0_NDFC_BW_8_BIT |
156 SDR0_CUST0_NDFC_ARE_MASK |
157 (0x80000000 >> (28 + CONFIG_SYS_NAND0_CS)) |
158 (0x80000000 >> (28 + CONFIG_SYS_NAND1_CS));
159 mtsdr(SDR0_CUST0, sdr0_cust0);
160
161 return 0;
162 }
163
164 int misc_init_r(void)
165 {
166 uint pbcr;
167 int size_val = 0;
168 u32 reg;
169 unsigned long usb2d0cr = 0;
170 unsigned long usb2phy0cr, usb2h0cr = 0;
171 unsigned long sdr0_pfc1;
172 unsigned long sdr0_srst0, sdr0_srst1;
173 int i, j;
174
175 /* adjust flash start and offset */
176 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
177 gd->bd->bi_flashoffset = 0;
178
179 mtdcr(ebccfga, pb0cr);
180 pbcr = mfdcr(ebccfgd);
181 size_val = ffs(gd->bd->bi_flashsize) - 21;
182 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
183 mtdcr(ebccfga, pb0cr);
184 mtdcr(ebccfgd, pbcr);
185
186 /*
187 * Re-check to get correct base address
188 */
189 flash_get_size(gd->bd->bi_flashstart, 0);
190
191 /*
192 * USB suff...
193 */
194 /* SDR Setting */
195 mfsdr(SDR0_PFC1, sdr0_pfc1);
196 mfsdr(SDR0_USB0, usb2d0cr);
197 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
198 mfsdr(SDR0_USB2H0CR, usb2h0cr);
199
200 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
201 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
202 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
203 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
204 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
205 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
206 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
207 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
208 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
209 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
210
211 /* An 8-bit/60MHz interface is the only possible alternative
212 when connecting the Device to the PHY */
213 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
214 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
215
216 /* To enable the USB 2.0 Device function through the UTMI interface */
217 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
218
219 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
220 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
221
222 mtsdr(SDR0_PFC1, sdr0_pfc1);
223 mtsdr(SDR0_USB0, usb2d0cr);
224 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
225 mtsdr(SDR0_USB2H0CR, usb2h0cr);
226
227 /*
228 * Take USB out of reset:
229 * -Initial status = all cores are in reset
230 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
231 * -wait 1 ms
232 * -deassert reset to PHY
233 * -wait 1 ms
234 * -deassert reset to HOST
235 * -wait 4 ms
236 * -deassert all other resets
237 */
238 mfsdr(SDR0_SRST1, sdr0_srst1);
239 sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
240 SDR0_SRST1_P4OPB0 | \
241 SDR0_SRST1_OPBA2 | \
242 SDR0_SRST1_PLB42OPB1 | \
243 SDR0_SRST1_OPB2PLB40);
244 mtsdr(SDR0_SRST1, sdr0_srst1);
245 udelay(1000);
246
247 mfsdr(SDR0_SRST1, sdr0_srst1);
248 sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
249 mtsdr(SDR0_SRST1, sdr0_srst1);
250 udelay(1000);
251
252 mfsdr(SDR0_SRST0, sdr0_srst0);
253 sdr0_srst0 &= ~SDR0_SRST0_USB2H;
254 mtsdr(SDR0_SRST0, sdr0_srst0);
255 udelay(4000);
256
257 /* finally all the other resets */
258 mtsdr(SDR0_SRST1, 0x00000000);
259 mtsdr(SDR0_SRST0, 0x00000000);
260
261 printf("USB: Host(int phy)\n");
262
263 /*
264 * Clear PLB4A0_ACR[WRP]
265 * This fix will make the MAL burst disabling patch for the Linux
266 * EMAC driver obsolete.
267 */
268 reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
269 mtdcr(plb4_acr, reg);
270
271 /*
272 * release IO-RST#
273 * We have to wait at least 560ms until we may call usbhub_init
274 */
275 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
276 CONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS_GPIO1_IORST2N);
277
278 /*
279 * flash USR1/2 LEDs (600ms)
280 * This results in the necessary delay from IORST# until
281 * calling usbhub_init will succeed
282 */
283 for (j = 0; j < 3; j++) {
284 out_be32((void*)GPIO1_OR,
285 (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR2) |
286 CONFIG_SYS_GPIO1_LEDUSR1);
287
288 for (i = 0; i < 100; i++)
289 udelay(1000);
290
291 out_be32((void*)GPIO1_OR,
292 (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR1) |
293 CONFIG_SYS_GPIO1_LEDUSR2);
294
295 for (i = 0; i < 100; i++)
296 udelay(1000);
297 }
298
299 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
300 ~(CONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS_GPIO1_LEDUSR2));
301
302 if (usbhub_init())
303 du440_post_errors++;
304
305 if (dvi_init())
306 du440_post_errors++;
307
308 return 0;
309 }
310
311 int pld_revision(void)
312 {
313 out8(CONFIG_SYS_CPLD_BASE, 0x00);
314 return (int)(in8(CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK);
315 }
316
317 int board_revision(void)
318 {
319 int rpins = (int)((in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_HWVER_MASK)
320 >> CONFIG_SYS_GPIO1_HWVER_SHIFT);
321
322 return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
323 ((rpins & 4) >> 1) | ((rpins & 8) >> 3);
324 }
325
326 #if defined(CONFIG_SHOW_ACTIVITY)
327 void board_show_activity (ulong timestamp)
328 {
329 if ((timestamp % 100) == 0)
330 out_be32((void*)GPIO1_OR,
331 in_be32((void*)GPIO1_OR) ^ CONFIG_SYS_GPIO1_LEDUSR1);
332 }
333
334 void show_activity(int arg)
335 {
336 }
337 #endif /* CONFIG_SHOW_ACTIVITY */
338
339 int du440_phy_addr(int devnum)
340 {
341 if (board_revision() == 0)
342 return devnum;
343
344 return devnum + 1;
345 }
346
347 int checkboard(void)
348 {
349 char serno[32];
350
351 puts("Board: DU440");
352
353 if (getenv_r("serial#", serno, sizeof(serno)) > 0) {
354 puts(", serial# ");
355 puts(serno);
356 }
357
358 printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n",
359 board_revision(), pld_revision());
360 return (0);
361 }
362
363 /*
364 * pci_pre_init
365 *
366 * This routine is called just prior to registering the hose and gives
367 * the board the opportunity to check things. Returning a value of zero
368 * indicates that things are bad & PCI initialization should be aborted.
369 *
370 * Different boards may wish to customize the pci controller structure
371 * (add regions, override default access routines, etc) or perform
372 * certain pre-initialization actions.
373 */
374 #if defined(CONFIG_PCI)
375 int pci_pre_init(struct pci_controller *hose)
376 {
377 unsigned long addr;
378
379 /*
380 * Set priority for all PLB3 devices to 0.
381 * Set PLB3 arbiter to fair mode.
382 */
383 mfsdr(sdr_amp1, addr);
384 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
385 addr = mfdcr(plb3_acr);
386 mtdcr(plb3_acr, addr | 0x80000000);
387
388 /*
389 * Set priority for all PLB4 devices to 0.
390 */
391 mfsdr(sdr_amp0, addr);
392 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
393 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
394 mtdcr(plb4_acr, addr);
395
396 /*
397 * Set Nebula PLB4 arbiter to fair mode.
398 */
399 /* Segment0 */
400 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
401 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
402 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
403 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
404 mtdcr(plb0_acr, addr);
405
406 /* Segment1 */
407 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
408 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
409 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
410 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
411 mtdcr(plb1_acr, addr);
412
413 return 1;
414 }
415 #endif /* defined(CONFIG_PCI) */
416
417 /*
418 * pci_target_init
419 *
420 * The bootstrap configuration provides default settings for the pci
421 * inbound map (PIM). But the bootstrap config choices are limited and
422 * may not be sufficient for a given board.
423 */
424 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
425 void pci_target_init(struct pci_controller *hose)
426 {
427 /*
428 * Set up Direct MMIO registers
429 */
430 /*
431 * PowerPC440EPX PCI Master configuration.
432 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
433 * PLB address 0xA0000000-0xDFFFFFFF
434 * ==> PCI address 0xA0000000-0xDFFFFFFF
435 * Use byte reversed out routines to handle endianess.
436 * Make this region non-prefetchable.
437 */
438 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
439 /* - disabled b4 setting */
440 out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
441 out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
442 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
443 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
444 /* and enable region */
445
446 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
447 /* - disabled b4 setting */
448 out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
449 out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
450 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
451 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
452 /* and enable region */
453
454 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
455 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
456 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
457 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
458
459 /*
460 * Set up Configuration registers
461 */
462
463 /* Program the board's subsystem id/vendor id */
464 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
465 PCI_VENDOR_ID_ESDGMBH);
466 pci_write_config_word(0, PCI_SUBSYSTEM_ID, PCI_DEVICE_ID_DU440);
467
468 pci_write_config_word(0, PCI_CLASS_SUB_CODE, PCI_CLASS_BRIDGE_HOST);
469
470 /* Configure command register as bus master */
471 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
472
473 /* 240nS PCI clock */
474 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
475
476 /* No error reporting */
477 pci_write_config_word(0, PCI_ERREN, 0);
478
479 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
480
481 }
482 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
483
484 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
485 void pci_master_init(struct pci_controller *hose)
486 {
487 unsigned short temp_short;
488
489 /*
490 * Write the PowerPC440 EP PCI Configuration regs.
491 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
492 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
493 */
494 pci_read_config_word(0, PCI_COMMAND, &temp_short);
495 pci_write_config_word(0, PCI_COMMAND,
496 temp_short | PCI_COMMAND_MASTER |
497 PCI_COMMAND_MEMORY);
498 }
499 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
500
501 /*
502 * is_pci_host
503 *
504 * This routine is called to determine if a pci scan should be
505 * performed. With various hardware environments (especially cPCI and
506 * PPMC) it's insufficient to depend on the state of the arbiter enable
507 * bit in the strap register, or generic host/adapter assumptions.
508 *
509 * Rather than hard-code a bad assumption in the general 440 code, the
510 * 440 pci code requires the board to decide at runtime.
511 *
512 * Return 0 for adapter mode, non-zero for host (monarch) mode.
513 */
514 #if defined(CONFIG_PCI)
515 int is_pci_host(struct pci_controller *hose)
516 {
517 /* always configured as host. */
518 return (1);
519 }
520 #endif /* defined(CONFIG_PCI) */
521
522 int last_stage_init(void)
523 {
524 int e, i;
525
526 /* everyting is ok: turn on POST-LED */
527 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
528
529 /* slowly blink on errors and finally keep LED off */
530 for (e = 0; e < du440_post_errors; e++) {
531 out_be32((void*)GPIO1_OR,
532 in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
533
534 for (i = 0; i < 500; i++)
535 udelay(1000);
536
537 out_be32((void*)GPIO1_OR,
538 in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDPOST);
539
540 for (i = 0; i < 500; i++)
541 udelay(1000);
542 }
543
544 return 0;
545 }
546
547 #if defined(CONFIG_I2C_MULTI_BUS)
548 /*
549 * read field strength from I2C ADC
550 */
551 int dcf77_status(void)
552 {
553 unsigned int oldbus;
554 uchar u[2];
555 int mv;
556
557 oldbus = I2C_GET_BUS();
558 I2C_SET_BUS(1);
559
560 if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) {
561 I2C_SET_BUS(oldbus);
562 return -1;
563 }
564
565 mv = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024;
566
567 I2C_SET_BUS(oldbus);
568 return mv;
569 }
570
571 int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
572 {
573 int mv;
574 u32 pin, pinold;
575 unsigned long long t1, t2;
576 bd_t *bd = gd->bd;
577
578 printf("DCF77: ");
579 mv = dcf77_status();
580 if (mv > 0)
581 printf("signal=%d mV\n", mv);
582 else
583 printf("ERROR - no signal\n");
584
585 t1 = t2 = 0;
586 pinold = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
587 while (!ctrlc()) {
588 pin = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
589 if (pin && !pinold) { /* bit start */
590 t1 = get_ticks();
591 if (t2 && ((unsigned int)(t1 - t2) /
592 (bd->bi_procfreq / 1000) >= 1800))
593 printf("Start of minute\n");
594
595 t2 = t1;
596 }
597 if (t1 && !pin && pinold) { /* bit end */
598 printf("%5d\n", (unsigned int)(get_ticks() - t1) /
599 (bd->bi_procfreq / 1000));
600 }
601 pinold = pin;
602 }
603
604 printf("Abort\n");
605 return 0;
606 }
607 U_BOOT_CMD(
608 dcf77, 1, 1, do_dcf77,
609 "dcf77 - Check DCF77 receiver\n",
610 NULL
611 );
612
613 /*
614 * initialize USB hub via I2C1
615 */
616 int usbhub_init(void)
617 {
618 int reg;
619 int ret = 0;
620 unsigned int oldbus;
621 uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3,
622 0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64,
623 0x32};
624 uchar stcd;
625
626 printf("Hub: ");
627
628 oldbus = I2C_GET_BUS();
629 I2C_SET_BUS(1);
630
631 for (reg = 0; reg < sizeof(u); reg++)
632 if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) {
633 ret = -1;
634 break;
635 }
636
637 if (ret == 0) {
638 stcd = 0x03;
639 if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1))
640 ret = -1;
641 }
642
643 if (ret == 0)
644 printf("initialized\n");
645 else
646 printf("failed - cannot initialize USB hub\n");
647
648 I2C_SET_BUS(oldbus);
649 return ret;
650 }
651
652 int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
653 {
654 usbhub_init();
655 return 0;
656 }
657 U_BOOT_CMD(
658 hubinit, 1, 1, do_hubinit,
659 "hubinit - Initialize USB hub\n",
660 NULL
661 );
662 #endif /* CONFIG_I2C_MULTI_BUS */
663
664 #define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
665 int boot_eeprom_write (unsigned dev_addr,
666 unsigned offset,
667 uchar *buffer,
668 unsigned cnt)
669 {
670 unsigned end = offset + cnt;
671 unsigned blk_off;
672 int rcode = 0;
673
674 #if defined(CONFIG_SYS_EEPROM_WREN)
675 eeprom_write_enable(dev_addr, 1);
676 #endif
677 /*
678 * Write data until done or would cross a write page boundary.
679 * We must write the address again when changing pages
680 * because the address counter only increments within a page.
681 */
682
683 while (offset < end) {
684 unsigned alen, len;
685 unsigned maxlen;
686
687 uchar addr[2];
688
689 blk_off = offset & 0xFF; /* block offset */
690
691 addr[0] = offset >> 8; /* block number */
692 addr[1] = blk_off; /* block offset */
693 alen = 2;
694 addr[0] |= dev_addr; /* insert device address */
695
696 len = end - offset;
697
698 /*
699 * For a FRAM device there is no limit on the number of the
700 * bytes that can be ccessed with the single read or write
701 * operation.
702 */
703 #if defined(CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
704
705 #define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
706 #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
707
708 maxlen = BOOT_EEPROM_PAGE_SIZE -
709 BOOT_EEPROM_PAGE_OFFSET(blk_off);
710 #else
711 maxlen = 0x100 - blk_off;
712 #endif
713 if (maxlen > I2C_RXTX_LEN)
714 maxlen = I2C_RXTX_LEN;
715
716 if (len > maxlen)
717 len = maxlen;
718
719 if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0)
720 rcode = 1;
721
722 buffer += len;
723 offset += len;
724
725 #if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
726 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
727 #endif
728 }
729 #if defined(CONFIG_SYS_EEPROM_WREN)
730 eeprom_write_enable(dev_addr, 0);
731 #endif
732 return rcode;
733 }
734
735 int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
736 {
737 ulong sdsdp[4];
738
739 if (argc > 1) {
740 if (!strcmp(argv[1], "533")) {
741 printf("Bootstrapping for 533MHz\n");
742 sdsdp[0] = 0x87788252;
743 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
744 sdsdp[1] = 0x095fa030;
745 sdsdp[2] = 0x40082350;
746 sdsdp[3] = 0x0d050000;
747 } else if (!strcmp(argv[1], "533-66")) {
748 printf("Bootstrapping for 533MHz (66MHz PCI)\n");
749 sdsdp[0] = 0x87788252;
750 /* PLB-PCI-divider = 2 : sync PCI clock=66MHz */
751 sdsdp[1] = 0x0957a030;
752 sdsdp[2] = 0x40082350;
753 sdsdp[3] = 0x0d050000;
754 } else if (!strcmp(argv[1], "667")) {
755 printf("Bootstrapping for 667MHz\n");
756 sdsdp[0] = 0x8778a256;
757 /* PLB-PCI-divider = 4 : sync PCI clock=33MHz */
758 sdsdp[1] = 0x0947a030;
759 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz
760 * -> not working when overclocking 533MHz chips
761 * -> untested on 667MHz chips */
762 /* sdsdp[1]=0x095fa030; */
763 sdsdp[2] = 0x40082350;
764 sdsdp[3] = 0x0d050000;
765 } else if (!strcmp(argv[1], "667-166")) {
766 printf("Bootstrapping for 667-166MHz\n");
767 sdsdp[0] = 0x8778a252;
768 sdsdp[1] = 0x09d7a030;
769 sdsdp[2] = 0x40082350;
770 sdsdp[3] = 0x0d050000;
771 }
772 } else {
773 printf("Bootstrapping for 533MHz (default)\n");
774 sdsdp[0] = 0x87788252;
775 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
776 sdsdp[1] = 0x095fa030;
777 sdsdp[2] = 0x40082350;
778 sdsdp[3] = 0x0d050000;
779 }
780
781 printf("Writing boot EEPROM ...\n");
782 if (boot_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
783 0, (uchar*)sdsdp, 16) != 0)
784 printf("boot_eeprom_write failed\n");
785 else
786 printf("done (dump via 'i2c md 52 0.1 10')\n");
787
788 return 0;
789 }
790 U_BOOT_CMD(
791 sbe, 2, 0, do_setup_boot_eeprom,
792 "sbe - setup boot eeprom\n",
793 NULL
794 );
795
796 #if defined(CONFIG_SYS_EEPROM_WREN)
797 /*
798 * Input: <dev_addr> I2C address of EEPROM device to enable.
799 * <state> -1: deliver current state
800 * 0: disable write
801 * 1: enable write
802 * Returns: -1: wrong device address
803 * 0: dis-/en- able done
804 * 0/1: current state if <state> was -1.
805 */
806 int eeprom_write_enable (unsigned dev_addr, int state)
807 {
808 if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
809 (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr))
810 return -1;
811 else {
812 switch (state) {
813 case 1:
814 /* Enable write access, clear bit GPIO_SINT2. */
815 out_be32((void*)GPIO0_OR,
816 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_GPIO0_EP_EEP);
817 state = 0;
818 break;
819 case 0:
820 /* Disable write access, set bit GPIO_SINT2. */
821 out_be32((void*)GPIO0_OR,
822 in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO0_EP_EEP);
823 state = 0;
824 break;
825 default:
826 /* Read current status back. */
827 state = (0 == (in_be32((void*)GPIO0_OR) &
828 CONFIG_SYS_GPIO0_EP_EEP));
829 break;
830 }
831 }
832 return state;
833 }
834
835 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
836 {
837 int query = argc == 1;
838 int state = 0;
839
840 if (query) {
841 /* Query write access state. */
842 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
843 if (state < 0)
844 puts ("Query of write access state failed.\n");
845 else {
846 printf ("Write access for device 0x%0x is %sabled.\n",
847 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
848 state = 0;
849 }
850 } else {
851 if ('0' == argv[1][0]) {
852 /* Disable write access. */
853 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
854 } else {
855 /* Enable write access. */
856 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
857 }
858 if (state < 0)
859 puts ("Setup of write access state failed.\n");
860 }
861
862 return state;
863 }
864
865 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
866 "eepwren - Enable / disable / query EEPROM write access\n",
867 NULL);
868 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
869
870 static int got_pldirq;
871
872 static int pld_interrupt(u32 arg)
873 {
874 int rc = -1; /* not for us */
875 u8 status = in8(CONFIG_SYS_CPLD_BASE);
876
877 /* check for PLD interrupt */
878 if (status & PWR_INT_FLAG) {
879 /* reset this int */
880 out8(CONFIG_SYS_CPLD_BASE, 0);
881 rc = 0;
882 got_pldirq = 1; /* trigger backend */
883 }
884
885 return rc;
886 }
887
888 int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
889 {
890 got_pldirq = 0;
891
892 /* clear any pending interrupt */
893 out8(CONFIG_SYS_CPLD_BASE, 0);
894
895 irq_install_handler(CPLD_IRQ,
896 (interrupt_handler_t *)pld_interrupt, 0);
897
898 printf("Waiting ...\n");
899 while(!got_pldirq) {
900 /* Abort if ctrl-c was pressed */
901 if (ctrlc()) {
902 puts("\nAbort\n");
903 break;
904 }
905 }
906 if (got_pldirq) {
907 printf("Got interrupt!\n");
908 printf("Power %sready!\n",
909 in8(CONFIG_SYS_CPLD_BASE) & PWR_RDY ? "":"NOT ");
910 }
911
912 irq_free_handler(CPLD_IRQ);
913 return 0;
914 }
915 U_BOOT_CMD(
916 wpi, 1, 1, do_waitpwrirq,
917 "wpi - Wait for power change interrupt\n",
918 NULL
919 );
920
921 /*
922 * initialize DVI panellink transmitter
923 */
924 int dvi_init(void)
925 {
926 int i;
927 int ret = 0;
928 unsigned int oldbus;
929 uchar u[] = {0x08, 0x34,
930 0x09, 0x20,
931 0x0a, 0x90,
932 0x0c, 0x89,
933 0x08, 0x35};
934
935 printf("DVI: ");
936
937 oldbus = I2C_GET_BUS();
938 I2C_SET_BUS(0);
939
940 for (i = 0; i < sizeof(u); i += 2)
941 if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) {
942 ret = -1;
943 break;
944 }
945
946 if (ret == 0)
947 printf("initialized\n");
948 else
949 printf("failed - cannot initialize DVI transmitter\n");
950
951 I2C_SET_BUS(oldbus);
952 return ret;
953 }
954
955 int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
956 {
957 dvi_init();
958 return 0;
959 }
960 U_BOOT_CMD(
961 dviinit, 1, 1, do_dviinit,
962 "dviinit - Initialize DVI Panellink transmitter\n",
963 NULL
964 );
965
966 /*
967 * TODO: 'time' command might be useful for others as well.
968 * Move to 'common' directory.
969 */
970 int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
971 {
972 unsigned long long start, end;
973 char c, cmd[CONFIG_SYS_CBSIZE];
974 char *p, *d = cmd;
975 int ret, i;
976 ulong us;
977
978 for (i = 1; i < argc; i++) {
979 p = argv[i];
980
981 if (i > 1)
982 *d++ = ' ';
983
984 while ((c = *p++) != '\0') {
985 *d++ = c;
986 }
987 }
988 *d = '\0';
989
990 start = get_ticks();
991 ret = run_command (cmd, 0);
992 end = get_ticks();
993
994 printf("ticks=%ld\n", (ulong)(end - start));
995 us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
996 printf("usec=%ld\n", us);
997
998 return ret;
999 }
1000 U_BOOT_CMD(
1001 time, CONFIG_SYS_MAXARGS, 1, do_time,
1002 "time - run command and output execution time\n",
1003 NULL
1004 );
1005
1006 extern void video_hw_rectfill (
1007 unsigned int bpp, /* bytes per pixel */
1008 unsigned int dst_x, /* dest pos x */
1009 unsigned int dst_y, /* dest pos y */
1010 unsigned int dim_x, /* frame width */
1011 unsigned int dim_y, /* frame height */
1012 unsigned int color /* fill color */
1013 );
1014
1015 /*
1016 * graphics demo
1017 * draw rectangles using pseudorandom number generator
1018 * (see http://www.embedded.com/columns/technicalinsights/20900500)
1019 */
1020 unsigned int rprime = 9972;
1021 static unsigned int r;
1022 static unsigned int Y;
1023
1024 unsigned int prng(unsigned int max)
1025 {
1026 if (r == 0 || r == 1 || r == -1)
1027 r = rprime; /* keep from getting stuck */
1028
1029 r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */
1030 Y = (r >> 16) % max; /* choose upper bits and reduce */
1031 return Y;
1032 }
1033
1034 int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
1035 {
1036 unsigned int color;
1037 unsigned int x, y, dx, dy;
1038
1039 while (!ctrlc()) {
1040 x = prng(1280 - 1);
1041 y = prng(1024 - 1);
1042 dx = prng(1280- x - 1);
1043 dy = prng(1024 - y - 1);
1044 color = prng(0x10000);
1045 video_hw_rectfill(2, x, y, dx, dy, color);
1046 }
1047
1048 return 0;
1049 }
1050 U_BOOT_CMD(
1051 gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo,
1052 "gfxdemo - demo\n",
1053 NULL
1054 );
"Das U-Boot" Source Tree