board/esd/mecp5123/mecp5123.c

   1 /*
   2  * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
   3  * (C) Copyright 2009 Dave Srl www.dave.eu
   4  * (C) Copyright 2009 Stefan Roese <sr@denx.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/bitops.h>
  11 #include <command.h>
  12 #include <asm/io.h>
  13 #include <asm/processor.h>
  14 #include <asm/mpc512x.h>
  15 #include <fdt_support.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 int eeprom_write_enable(unsigned dev_addr, int state)
  20 {
  21         volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  22
  23         if (dev_addr != CONFIG_SYS_I2C_EEPROM_ADDR)
  24                 return -1;
  25
  26         if (state == 0)
  27                 setbits_be32(&im->gpio.gpdat, 0x00100000);
  28         else
  29                 clrbits_be32(&im->gpio.gpdat, 0x00100000);
  30
  31         return 0;
  32 }
  33
  34 int board_early_init_f(void)
  35 {
  36         volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  37         int i;
  38
  39         /*
  40          * Initialize Local Window for boot access
  41          */
  42         out_be32(&im->sysconf.lpbaw,
  43                  CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
  44         sync_law(&im->sysconf.lpbaw);
  45
  46         /*
  47          * Configure MSCAN clocks
  48          */
  49         for (i=0; i<4; ++i) {
  50                 out_be32(&im->clk.msccr[i], 0x00300000);
  51                 out_be32(&im->clk.msccr[i], 0x00310000);
  52         }
  53
  54         /*
  55          * Configure GPIO's
  56          */
  57         clrbits_be32(&im->gpio.gpodr, 0x000000e0);
  58         clrbits_be32(&im->gpio.gpdir, 0x00ef0000);
  59         setbits_be32(&im->gpio.gpdir, 0x001000e0);
  60         setbits_be32(&im->gpio.gpdat, 0x00100000);
  61
  62         return 0;
  63 }
  64
  65 int initdram(void)
  66 {
  67         gd->ram_size = get_ram_size(0, fixed_sdram(NULL, NULL, 0));
  68
  69         return 0;
  70 }
  71
  72 int misc_init_r(void)
  73 {
  74         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  75         u32 val;
  76
  77         /*
  78          * Optimize access to profibus chip (VPC3) on the local bus
  79          */
  80
  81         /*
  82          * Select 1:1 for LPC_DIV
  83          */
  84         val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK;
  85         out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT));
  86
  87         /*
  88          * Configure LPC Chips Select Deadcycle Control Register
  89          * CS0 - device can drive data 2 clock cycle(s) after CS deassertion
  90          * CS1 - device can drive data 1 clock cycle(s) after CS deassertion
  91          */
  92         clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
  93         setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
  94
  95         /*
  96          * Configure LPC Chips Select Holdcycle Control Register
  97          * CS0 - data is valid 2 clock cycle(s) after CS deassertion
  98          * CS1 - data is valid 1 clock cycle(s) after CS deassertion
  99          */
 100         clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
 101         setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
 102
 103         return 0;
 104 }
 105
 106 static iopin_t ioregs_init[] = {
 107         /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
 108         {
 109                 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
 110                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 111                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 112         },
 113         /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
 114         {
 115                 offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
 116                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 117                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 118         },
 119         /* FUNC1=SELECT LPC_CS1 */
 120         {
 121                 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
 122                 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 123                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 124         },
 125         /* FUNC3=SELECT PSC5_2 */
 126         {
 127                 offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0,
 128                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 129                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 130         },
 131         /* FUNC3=SELECT PSC5_3 */
 132         {
 133                 offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0,
 134                 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 135                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 136         },
 137         /* FUNC3=SELECT PSC7_3 */
 138         {
 139                 offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0,
 140                 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 141                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 142         },
 143         /* FUNC3=SELECT PSC9_0 */
 144         {
 145                 offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0,
 146                 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 147                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 148         },
 149         /* FUNC3=SELECT PSC10_0 */
 150         {
 151                 offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0,
 152                 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 153                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 154         },
 155         /* FUNC3=SELECT PSC10_3 */
 156         {
 157                 offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0,
 158                 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 159                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 160         },
 161         /* FUNC3=SELECT PSC11_0 */
 162         {
 163                 offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0,
 164                 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 165                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 166         },
 167         /* FUNC0=SELECT IRQ0 */
 168         {
 169                 offsetof(struct ioctrl512x, io_control_irq0), 4, 0,
 170                 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 171                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 172         }
 173 };
 174
 175 static iopin_t rev2_silicon_pci_ioregs_init[] = {
 176         /* FUNC0=PCI Sets next 54 to PCI pads */
 177         {
 178                 offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
 179                 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
 180         }
 181 };
 182
 183 int checkboard(void)
 184 {
 185         volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 186         u32 spridr;
 187
 188         puts("Board: MECP_5123\n");
 189
 190         /*
 191          * Initialize function mux & slew rate IO inter alia on IO
 192          * Pins
 193          */
 194         iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
 195
 196         spridr = in_be32(&im->sysconf.spridr);
 197         if (SVR_MJREV(spridr) >= 2)
 198                 iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
 199
 200         return 0;
 201 }
 202
 203 #ifdef CONFIG_OF_BOARD_SETUP
 204 int ft_board_setup(void *blob, bd_t *bd)
 205 {
 206         ft_cpu_setup(blob, bd);
 207
 208         return 0;
 209 }
 210 #endif /* CONFIG_OF_BOARD_SETUP */