board/esd/pci405/pci405.c

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <command.h>
  27 #include <malloc.h>
  28 #include <pci.h>
  29 #include <405gp_pci.h>
  30
  31 #include "pci405.h"
  32
  33
  34 /* Prototypes */
  35 int gunzip(void *, int, unsigned char *, unsigned long *);
  36 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);/*cmd_boot.c*/
  37 unsigned long fpga_done_state(void);
  38 unsigned long fpga_init_state(void);
  39
  40 #if 0
  41 #define FPGA_DEBUG
  42 #endif
  43
  44 /* predefine these here */
  45 #define FPGA_DONE_STATE (fpga_done_state())
  46 #define FPGA_INIT_STATE (fpga_init_state())
  47
  48 /* fpga configuration data - generated by bin2cc */
  49 const unsigned char fpgadata[] =
  50 {
  51 #include "fpgadata.c"
  52 };
  53
  54 /*
  55  * include common fpga code (for esd boards)
  56  */
  57 #include "../common/fpga.c"
  58
  59 #define FPGA_DONE_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_DONE)
  60 #define FPGA_DONE_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_DONE_V12)
  61
  62 #define FPGA_INIT_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_INIT)
  63 #define FPGA_INIT_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_INIT_V12)
  64
  65
  66 int board_revision(void)
  67 {
  68         unsigned long cntrl0Reg;
  69         unsigned long value;
  70
  71         /*
  72          * Get version of PCI405 board from GPIO's
  73          */
  74
  75         /*
  76          * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
  77          */
  78         cntrl0Reg = mfdcr(cntrl0);
  79         mtdcr(cntrl0, cntrl0Reg | 0x03000000);
  80         out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00100200);
  81         out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00100200);
  82         udelay(1000);                   /* wait some time before reading input */
  83         value = in32(GPIO0_IR) & 0x00100200;       /* get config bits */
  84
  85         /*
  86          * Restore GPIO settings
  87          */
  88         mtdcr(cntrl0, cntrl0Reg);
  89
  90         switch (value) {
  91         case 0x00100200:
  92                 /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
  93                 return 1;
  94         case 0x00000200:
  95                 /* CS2==0 && IRQ5==1 -> version 1.2 */
  96                 return 2;
  97         case 0x00000000:
  98                 /* CS2==0 && IRQ5==0 -> version 1.3 */
  99                 return 3;
 100 #if 0 /* not yet manufactured ! */
 101         case 0x00100000:
 102                 /* CS2==1 && IRQ5==0 -> version 1.4 */
 103                 return 4;
 104 #endif
 105         default:
 106                 /* should not be reached! */
 107                 return 0;
 108         }
 109 }
 110
 111
 112 unsigned long fpga_done_state(void)
 113 {
 114         DECLARE_GLOBAL_DATA_PTR;
 115
 116         if (gd->board_type < 2) {
 117                 return FPGA_DONE_STATE_V11;
 118         } else {
 119                 return FPGA_DONE_STATE_V12;
 120         }
 121 }
 122
 123
 124 unsigned long fpga_init_state(void)
 125 {
 126         DECLARE_GLOBAL_DATA_PTR;
 127
 128         if (gd->board_type < 2) {
 129                 return FPGA_INIT_STATE_V11;
 130         } else {
 131                 return FPGA_INIT_STATE_V12;
 132         }
 133 }
 134
 135
 136 int board_early_init_f (void)
 137 {
 138         unsigned long cntrl0Reg;
 139
 140         /*
 141          * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
 142          */
 143         out32(GPIO0_ODR, 0x00000000);        /* no open drain pins      */
 144         out32(GPIO0_TCR, CFG_FPGA_PRG);      /* setup for output        */
 145         out32(GPIO0_OR,  CFG_FPGA_PRG);      /* set output pins to high */
 146         out32(GPIO0_OR, 0);                  /* pull prg low            */
 147
 148         /*
 149          * IRQ 0-15  405GP internally generated; active high; level sensitive
 150          * IRQ 16    405GP internally generated; active low; level sensitive
 151          * IRQ 17-24 RESERVED
 152          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
 153          * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
 154          * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive
 155          * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive
 156          * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
 157          * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
 158          * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
 159          */
 160         mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
 161         mtdcr(uicer, 0x00000000);        /* disable all ints */
 162         mtdcr(uiccr, 0x00000000);        /* set all to be non-critical*/
 163         mtdcr(uicpr, 0xFFFFFF80);        /* set int polarities */
 164         mtdcr(uictr, 0x10000000);        /* set int trigger levels */
 165         mtdcr(uicvcr, 0x00000001);       /* set vect base=0,INT0 highest priority*/
 166         mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
 167
 168         /*
 169          * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
 170          */
 171         cntrl0Reg = mfdcr(cntrl0);
 172         mtdcr(cntrl0, cntrl0Reg | 0x00008000);
 173
 174         /*
 175          * Setup GPIO pins (CS6+CS7 as GPIO)
 176          */
 177         mtdcr(cntrl0, cntrl0Reg | 0x00300000);
 178
 179         /*
 180          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
 181          */
 182         mtebc (epcr, 0xa8400000); /* ebc always driven */
 183
 184         return 0;
 185 }
 186
 187
 188 /* ------------------------------------------------------------------------- */
 189
 190 int misc_init_f (void)
 191 {
 192         return 0;  /* dummy implementation */
 193 }
 194
 195
 196 int misc_init_r (void)
 197 {
 198         unsigned char *dst;
 199         ulong len = sizeof(fpgadata);
 200         int status;
 201         int index;
 202         int i;
 203         unsigned int *ptr;
 204         unsigned int *magic;
 205
 206         /*
 207          * On PCI-405 the environment is saved in eeprom!
 208          * FPGA can be gzip compressed (malloc) and booted this late.
 209          */
 210
 211         dst = malloc(CFG_FPGA_MAX_SIZE);
 212         if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 213                 printf ("GUNZIP ERROR - must RESET board to recover\n");
 214                 do_reset (NULL, 0, 0, NULL);
 215         }
 216
 217         status = fpga_boot(dst, len);
 218         if (status != 0) {
 219                 printf("\nFPGA: Booting failed ");
 220                 switch (status) {
 221                 case ERROR_FPGA_PRG_INIT_LOW:
 222                         printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
 223                         break;
 224                 case ERROR_FPGA_PRG_INIT_HIGH:
 225                         printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
 226                         break;
 227                 case ERROR_FPGA_PRG_DONE:
 228                         printf("(Timeout: DONE not high after programming FPGA)\n ");
 229                         break;
 230                 }
 231
 232                 /* display infos on fpgaimage */
 233                 index = 15;
 234                 for (i=0; i<4; i++) {
 235                         len = dst[index];
 236                         printf("FPGA: %s\n", &(dst[index+1]));
 237                         index += len+3;
 238                 }
 239                 putc ('\n');
 240                 /* delayed reboot */
 241                 for (i=20; i>0; i--) {
 242                         printf("Rebooting in %2d seconds \r",i);
 243                         for (index=0;index<1000;index++)
 244                                 udelay(1000);
 245                 }
 246                 putc ('\n');
 247                 do_reset(NULL, 0, 0, NULL);
 248         }
 249
 250         puts("FPGA:  ");
 251
 252         /* display infos on fpgaimage */
 253         index = 15;
 254         for (i=0; i<4; i++) {
 255                 len = dst[index];
 256                 printf("%s ", &(dst[index+1]));
 257                 index += len+3;
 258         }
 259         putc ('\n');
 260
 261         /*
 262          * Reset FPGA via FPGA_DATA pin
 263          */
 264         SET_FPGA(FPGA_PRG | FPGA_CLK);
 265         udelay(1000); /* wait 1ms */
 266         SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 267         udelay(1000); /* wait 1ms */
 268
 269         /*
 270          * Check if magic for pci reconfig is written
 271          */
 272         magic = (unsigned int *)0x00000004;
 273         if (*magic == PCI_RECONFIG_MAGIC) {
 274                 /*
 275                  * Rewrite pci config regs (only after soft-reset with magic set)
 276                  */
 277                 ptr = (unsigned int *)PCI_REGS_ADDR;
 278                 if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
 279                         puts("Restoring PCI Configurations Regs!\n");
 280                         ptr = (unsigned int *)PCI_REGS_ADDR + 1;
 281                         for (i=0; i<0x40; i+=4) {
 282                                 pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
 283                         }
 284                 }
 285                 mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
 286
 287                 *magic = 0;      /* clear pci reconfig magic again */
 288         }
 289
 290 #if 1 /* test-only */
 291         /*
 292          * Decrease PLB latency timeout and reduce priority of the PCI bridge master
 293          */
 294 #define PCI0_BRDGOPT1 0x4a
 295         pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
 296 /*      pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f60);   */
 297
 298 #define plb0_acr      0x87
 299         /*
 300          * Enable fairness and high bus utilization
 301          */
 302         mtdcr(plb0_acr, 0x98000000);
 303
 304 #if 0 /* test-only */
 305         printf("CCR0=%08x\n", mfspr(ccr0)); /* test-only */
 306 /*      mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00100000);   */
 307         mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00000000);
 308 #endif
 309 /*      printf("CCR0=%08x\n", mfspr(ccr0)); */ /* test-only */
 310 #endif
 311
 312         free(dst);
 313         return (0);
 314 }
 315
 316
 317 /*
 318  * Check Board Identity:
 319  */
 320
 321 int checkboard (void)
 322 {
 323         DECLARE_GLOBAL_DATA_PTR;
 324
 325         char str[64];
 326         int i = getenv_r ("serial#", str, sizeof(str));
 327
 328         puts ("Board: ");
 329
 330         if (i == -1) {
 331                 puts ("### No HW ID - assuming PCI405");
 332         } else {
 333                 puts (str);
 334         }
 335
 336         gd->board_type = board_revision();
 337         printf(" (Rev 1.%ld", gd->board_type);
 338
 339         if (gd->board_type >= 2) {
 340                 unsigned long cntrl0Reg;
 341                 unsigned long value;
 342
 343                 /*
 344                  * Setup GPIO pins (Trace/GPIO1 to GPIO)
 345                  */
 346                 cntrl0Reg = mfdcr(cntrl0);
 347                 mtdcr(cntrl0, cntrl0Reg & ~0x08000000);
 348                 out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x40000000);
 349                 out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x40000000);
 350                 udelay(1000);                   /* wait some time before reading input */
 351                 value = in32(GPIO0_IR) & 0x40000000;       /* get config bits */
 352                 if (value) {
 353                         puts(", 33 MHz PCI");
 354                 } else {
 355                         puts(", 66 Mhz PCI");
 356                 }
 357         }
 358
 359         puts(")\n");
 360
 361         return 0;
 362 }
 363
 364 /* ------------------------------------------------------------------------- */
 365
 366 long int initdram (int board_type)
 367 {
 368         unsigned long val;
 369
 370         mtdcr(memcfga, mem_mb0cf);
 371         val = mfdcr(memcfgd);
 372
 373 #if 0
 374         printf("\nmb0cf=%x\n", val); /* test-only */
 375         printf("strap=%x\n", mfdcr(strap)); /* test-only */
 376 #endif
 377
 378 #if 0 /* test-only: all PCI405 version must report 16mb */
 379         return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 380 #else
 381         return (16*1024*1024);
 382 #endif
 383 }
 384
 385 /* ------------------------------------------------------------------------- */
 386
 387 int testdram (void)
 388 {
 389         /* TODO: XXX XXX XXX */
 390         printf ("test: 16 MB - ok\n");
 391
 392         return (0);
 393 }
 394
 395 /* ------------------------------------------------------------------------- */
 396 int wpeeprom(int wp)
 397 {
 398         int wp_state = wp;
 399         volatile unsigned char *uart1_mcr = (volatile unsigned char *)0xef600404;
 400
 401         if (wp == 1) {
 402                 *uart1_mcr &= ~0x02;
 403         } else if (wp == 0) {
 404                 *uart1_mcr |= 0x02;
 405         } else {
 406                 if (*uart1_mcr & 0x02) {
 407                         wp_state = 0;
 408                 } else {
 409                         wp_state = 1;
 410                 }
 411         }
 412         return wp_state;
 413 }
 414
 415 int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 416 {
 417         int wp = -1;
 418         if (argc >= 2) {
 419                 if (argv[1][0] == '1') {
 420                         wp = 1;
 421                 } else if (argv[1][0] == '0') {
 422                         wp = 0;
 423                 }
 424         }
 425
 426         wp = wpeeprom(wp);
 427         printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
 428         return 0;
 429 }
 430
 431 U_BOOT_CMD(
 432         wpeeprom,       2,      1,      do_wpeeprom,
 433         "wpeeprom - Check/Enable/Disable I2C EEPROM write protection\n",
 434         "wpeeprom\n"
 435         "    - check I2C EEPROM write protection state\n"
 436         "wpeeprom 1\n"
 437         "    - enable I2C EEPROM write protection\n"
 438         "wpeeprom 0\n"
 439         "    - disable I2C EEPROM write protection\n"
 440         );