board/esd/pci405/pci405.c

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <command.h>
  27 #include <malloc.h>
  28 #include <pci.h>
  29 #include <asm/4xx_pci.h>
  30 #include <asm/io.h>
  31
  32 #include "pci405.h"
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 /* Prototypes */
  37 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
  38 unsigned long fpga_done_state(void);
  39 unsigned long fpga_init_state(void);
  40
  41 #if 0
  42 #define FPGA_DEBUG
  43 #endif
  44
  45 /* predefine these here */
  46 #define FPGA_DONE_STATE (fpga_done_state())
  47 #define FPGA_INIT_STATE (fpga_init_state())
  48
  49 /* fpga configuration data - generated by bin2cc */
  50 const unsigned char fpgadata[] =
  51 {
  52 #include "fpgadata.c"
  53 };
  54
  55 /*
  56  * include common fpga code (for esd boards)
  57  */
  58 #include "../common/fpga.c"
  59
  60 #define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
  61 #define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
  62
  63 #define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
  64 #define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
  65
  66
  67 int board_revision(void)
  68 {
  69         unsigned long CPC0_CR0Reg;
  70         unsigned long value;
  71
  72         /*
  73          * Get version of PCI405 board from GPIO's
  74          */
  75
  76         /*
  77          * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
  78          */
  79         CPC0_CR0Reg = mfdcr(CPC0_CR0);
  80         mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
  81         out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
  82         out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
  83         udelay(1000);                   /* wait some time before reading input */
  84         value = in_be32((void*)GPIO0_IR) & 0x00100200;       /* get config bits */
  85
  86         /*
  87          * Restore GPIO settings
  88          */
  89         mtdcr(CPC0_CR0, CPC0_CR0Reg);
  90
  91         switch (value) {
  92         case 0x00100200:
  93                 /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
  94                 return 1;
  95         case 0x00000200:
  96                 /* CS2==0 && IRQ5==1 -> version 1.2 */
  97                 return 2;
  98         case 0x00000000:
  99                 /* CS2==0 && IRQ5==0 -> version 1.3 */
 100                 return 3;
 101 #if 0 /* not yet manufactured ! */
 102         case 0x00100000:
 103                 /* CS2==1 && IRQ5==0 -> version 1.4 */
 104                 return 4;
 105 #endif
 106         default:
 107                 /* should not be reached! */
 108                 return 0;
 109         }
 110 }
 111
 112
 113 unsigned long fpga_done_state(void)
 114 {
 115         if (gd->board_type < 2) {
 116                 return FPGA_DONE_STATE_V11;
 117         } else {
 118                 return FPGA_DONE_STATE_V12;
 119         }
 120 }
 121
 122
 123 unsigned long fpga_init_state(void)
 124 {
 125         if (gd->board_type < 2) {
 126                 return FPGA_INIT_STATE_V11;
 127         } else {
 128                 return FPGA_INIT_STATE_V12;
 129         }
 130 }
 131
 132
 133 int board_early_init_f (void)
 134 {
 135         unsigned long CPC0_CR0Reg;
 136
 137         /*
 138          * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
 139          */
 140         out_be32((void*)GPIO0_ODR, 0x00000000);        /* no open drain pins      */
 141         out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output        */
 142         out_be32((void*)GPIO0_OR,  CONFIG_SYS_FPGA_PRG);      /* set output pins to high */
 143         out_be32((void*)GPIO0_OR, 0);                  /* pull prg low            */
 144
 145         /*
 146          * IRQ 0-15  405GP internally generated; active high; level sensitive
 147          * IRQ 16    405GP internally generated; active low; level sensitive
 148          * IRQ 17-24 RESERVED
 149          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
 150          * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
 151          * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive
 152          * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive
 153          * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
 154          * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
 155          * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
 156          */
 157         mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
 158         mtdcr(UIC0ER, 0x00000000);        /* disable all ints */
 159         mtdcr(UIC0CR, 0x00000000);        /* set all to be non-critical*/
 160         mtdcr(UIC0PR, 0xFFFFFF80);        /* set int polarities */
 161         mtdcr(UIC0TR, 0x10000000);        /* set int trigger levels */
 162         mtdcr(UIC0VCR, 0x00000001);       /* set vect base=0,INT0 highest priority*/
 163         mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
 164
 165         /*
 166          * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
 167          */
 168         CPC0_CR0Reg = mfdcr(CPC0_CR0);
 169         mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000);
 170
 171         /*
 172          * Setup GPIO pins (CS6+CS7 as GPIO)
 173          */
 174         mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
 175
 176         /*
 177          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
 178          */
 179         mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
 180
 181         return 0;
 182 }
 183
 184 int misc_init_r (void)
 185 {
 186         unsigned char *dst;
 187         ulong len = sizeof(fpgadata);
 188         int status;
 189         int index;
 190         int i;
 191         unsigned int *ptr;
 192         unsigned int *magic;
 193
 194         /*
 195          * On PCI-405 the environment is saved in eeprom!
 196          * FPGA can be gzip compressed (malloc) and booted this late.
 197          */
 198
 199         dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
 200         if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 201                 printf ("GUNZIP ERROR - must RESET board to recover\n");
 202                 do_reset (NULL, 0, 0, NULL);
 203         }
 204
 205         status = fpga_boot(dst, len);
 206         if (status != 0) {
 207                 printf("\nFPGA: Booting failed ");
 208                 switch (status) {
 209                 case ERROR_FPGA_PRG_INIT_LOW:
 210                         printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
 211                         break;
 212                 case ERROR_FPGA_PRG_INIT_HIGH:
 213                         printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
 214                         break;
 215                 case ERROR_FPGA_PRG_DONE:
 216                         printf("(Timeout: DONE not high after programming FPGA)\n ");
 217                         break;
 218                 }
 219
 220                 /* display infos on fpgaimage */
 221                 index = 15;
 222                 for (i=0; i<4; i++) {
 223                         len = dst[index];
 224                         printf("FPGA: %s\n", &(dst[index+1]));
 225                         index += len+3;
 226                 }
 227                 putc ('\n');
 228                 /* delayed reboot */
 229                 for (i=20; i>0; i--) {
 230                         printf("Rebooting in %2d seconds \r",i);
 231                         for (index=0;index<1000;index++)
 232                                 udelay(1000);
 233                 }
 234                 putc ('\n');
 235                 do_reset(NULL, 0, 0, NULL);
 236         }
 237
 238         puts("FPGA:  ");
 239
 240         /* display infos on fpgaimage */
 241         index = 15;
 242         for (i=0; i<4; i++) {
 243                 len = dst[index];
 244                 printf("%s ", &(dst[index+1]));
 245                 index += len+3;
 246         }
 247         putc ('\n');
 248
 249         /*
 250          * Reset FPGA via FPGA_DATA pin
 251          */
 252         SET_FPGA(FPGA_PRG | FPGA_CLK);
 253         udelay(1000); /* wait 1ms */
 254         SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 255         udelay(1000); /* wait 1ms */
 256
 257         /*
 258          * Check if magic for pci reconfig is written
 259          */
 260         magic = (unsigned int *)0x00000004;
 261         if (*magic == PCI_RECONFIG_MAGIC) {
 262                 /*
 263                  * Rewrite pci config regs (only after soft-reset with magic set)
 264                  */
 265                 ptr = (unsigned int *)PCI_REGS_ADDR;
 266                 if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
 267                         puts("Restoring PCI Configurations Regs!\n");
 268                         ptr = (unsigned int *)PCI_REGS_ADDR + 1;
 269                         for (i=0; i<0x40; i+=4) {
 270                                 pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
 271                         }
 272                 }
 273                 mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
 274
 275                 *magic = 0;      /* clear pci reconfig magic again */
 276         }
 277
 278         /*
 279          * Decrease PLB latency timeout and reduce priority of the PCI bridge master
 280          */
 281 #define PCI0_BRDGOPT1 0x4a
 282         pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
 283
 284 #define PLB0_ACR      0x87
 285         /*
 286          * Enable fairness and high bus utilization
 287          */
 288         mtdcr(PLB0_ACR, 0x98000000);
 289
 290         free(dst);
 291         return (0);
 292 }
 293
 294
 295 /*
 296  * Check Board Identity:
 297  */
 298 int checkboard (void)
 299 {
 300         char str[64];
 301         int i = getenv_r ("serial#", str, sizeof(str));
 302
 303         puts ("Board: ");
 304
 305         if (i == -1) {
 306                 puts ("### No HW ID - assuming PCI405");
 307         } else {
 308                 puts (str);
 309         }
 310
 311         gd->board_type = board_revision();
 312         printf(" (Rev 1.%ld", gd->board_type);
 313
 314         if (gd->board_type >= 2) {
 315                 unsigned long CPC0_CR0Reg;
 316                 unsigned long value;
 317
 318                 /*
 319                  * Setup GPIO pins (Trace/GPIO1 to GPIO)
 320                  */
 321                 CPC0_CR0Reg = mfdcr(CPC0_CR0);
 322                 mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000);
 323                 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
 324                 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
 325                 udelay(1000);                   /* wait some time before reading input */
 326                 value = in_be32((void*)GPIO0_IR) & 0x40000000;       /* get config bits */
 327                 if (value) {
 328                         puts(", 33 MHz PCI");
 329                 } else {
 330                         puts(", 66 MHz PCI");
 331                 }
 332         }
 333
 334         puts(")\n");
 335
 336         return 0;
 337 }
 338
 339 /* ------------------------------------------------------------------------- */
 340 #define UART1_MCR 0xef600404
 341 int wpeeprom(int wp)
 342 {
 343         int wp_state = wp;
 344
 345         if (wp == 1) {
 346                 out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02);
 347         } else if (wp == 0) {
 348                 out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02);
 349         } else {
 350                 if (in_8((void *)UART1_MCR) & 0x02) {
 351                         wp_state = 0;
 352                 } else {
 353                         wp_state = 1;
 354                 }
 355         }
 356         return wp_state;
 357 }
 358
 359 int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 360 {
 361         int wp = -1;
 362         if (argc >= 2) {
 363                 if (argv[1][0] == '1') {
 364                         wp = 1;
 365                 } else if (argv[1][0] == '0') {
 366                         wp = 0;
 367                 }
 368         }
 369
 370         wp = wpeeprom(wp);
 371         printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
 372         return 0;
 373 }
 374
 375 U_BOOT_CMD(
 376         wpeeprom,       2,      1,      do_wpeeprom,
 377         "Check/Enable/Disable I2C EEPROM write protection",
 378         "wpeeprom\n"
 379         "    - check I2C EEPROM write protection state\n"
 380         "wpeeprom 1\n"
 381         "    - enable I2C EEPROM write protection\n"
 382         "wpeeprom 0\n"
 383         "    - disable I2C EEPROM write protection"
 384 );