board/esd/pci405/pci405.c

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/processor.h>
  10 #include <command.h>
  11 #include <malloc.h>
  12 #include <pci.h>
  13 #include <asm/4xx_pci.h>
  14 #include <asm/io.h>
  15
  16 #include "pci405.h"
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 /* Prototypes */
  21 unsigned long fpga_done_state(void);
  22 unsigned long fpga_init_state(void);
  23
  24 #if 0
  25 #define FPGA_DEBUG
  26 #endif
  27
  28 /* predefine these here */
  29 #define FPGA_DONE_STATE (fpga_done_state())
  30 #define FPGA_INIT_STATE (fpga_init_state())
  31
  32 /* fpga configuration data - generated by bin2cc */
  33 const unsigned char fpgadata[] =
  34 {
  35 #include "fpgadata.c"
  36 };
  37
  38 /*
  39  * include common fpga code (for esd boards)
  40  */
  41 #include "../common/fpga.c"
  42
  43 #define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
  44 #define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
  45
  46 #define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
  47 #define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
  48
  49
  50 int board_revision(void)
  51 {
  52         unsigned long CPC0_CR0Reg;
  53         unsigned long value;
  54
  55         /*
  56          * Get version of PCI405 board from GPIO's
  57          */
  58
  59         /*
  60          * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
  61          */
  62         CPC0_CR0Reg = mfdcr(CPC0_CR0);
  63         mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
  64         out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
  65         out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
  66         udelay(1000);                   /* wait some time before reading input */
  67         value = in_be32((void*)GPIO0_IR) & 0x00100200;       /* get config bits */
  68
  69         /*
  70          * Restore GPIO settings
  71          */
  72         mtdcr(CPC0_CR0, CPC0_CR0Reg);
  73
  74         switch (value) {
  75         case 0x00100200:
  76                 /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
  77                 return 1;
  78         case 0x00000200:
  79                 /* CS2==0 && IRQ5==1 -> version 1.2 */
  80                 return 2;
  81         case 0x00000000:
  82                 /* CS2==0 && IRQ5==0 -> version 1.3 */
  83                 return 3;
  84 #if 0 /* not yet manufactured ! */
  85         case 0x00100000:
  86                 /* CS2==1 && IRQ5==0 -> version 1.4 */
  87                 return 4;
  88 #endif
  89         default:
  90                 /* should not be reached! */
  91                 return 0;
  92         }
  93 }
  94
  95
  96 unsigned long fpga_done_state(void)
  97 {
  98         if (gd->board_type < 2) {
  99                 return FPGA_DONE_STATE_V11;
 100         } else {
 101                 return FPGA_DONE_STATE_V12;
 102         }
 103 }
 104
 105
 106 unsigned long fpga_init_state(void)
 107 {
 108         if (gd->board_type < 2) {
 109                 return FPGA_INIT_STATE_V11;
 110         } else {
 111                 return FPGA_INIT_STATE_V12;
 112         }
 113 }
 114
 115
 116 int board_early_init_f (void)
 117 {
 118         unsigned long CPC0_CR0Reg;
 119
 120         /*
 121          * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
 122          */
 123         out_be32((void*)GPIO0_ODR, 0x00000000);        /* no open drain pins      */
 124         out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output        */
 125         out_be32((void*)GPIO0_OR,  CONFIG_SYS_FPGA_PRG);      /* set output pins to high */
 126         out_be32((void*)GPIO0_OR, 0);                  /* pull prg low            */
 127
 128         /*
 129          * IRQ 0-15  405GP internally generated; active high; level sensitive
 130          * IRQ 16    405GP internally generated; active low; level sensitive
 131          * IRQ 17-24 RESERVED
 132          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
 133          * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
 134          * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive
 135          * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive
 136          * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
 137          * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
 138          * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
 139          */
 140         mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
 141         mtdcr(UIC0ER, 0x00000000);        /* disable all ints */
 142         mtdcr(UIC0CR, 0x00000000);        /* set all to be non-critical*/
 143         mtdcr(UIC0PR, 0xFFFFFF80);        /* set int polarities */
 144         mtdcr(UIC0TR, 0x10000000);        /* set int trigger levels */
 145         mtdcr(UIC0VCR, 0x00000001);       /* set vect base=0,INT0 highest priority*/
 146         mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
 147
 148         /*
 149          * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
 150          */
 151         CPC0_CR0Reg = mfdcr(CPC0_CR0);
 152         mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000);
 153
 154         /*
 155          * Setup GPIO pins (CS6+CS7 as GPIO)
 156          */
 157         mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
 158
 159         /*
 160          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
 161          */
 162         mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
 163
 164         return 0;
 165 }
 166
 167 int misc_init_r (void)
 168 {
 169         unsigned char *dst;
 170         ulong len = sizeof(fpgadata);
 171         int status;
 172         int index;
 173         int i;
 174         unsigned int *ptr;
 175         unsigned int *magic;
 176
 177         /*
 178          * On PCI-405 the environment is saved in eeprom!
 179          * FPGA can be gzip compressed (malloc) and booted this late.
 180          */
 181
 182         dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
 183         if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 184                 printf ("GUNZIP ERROR - must RESET board to recover\n");
 185                 do_reset (NULL, 0, 0, NULL);
 186         }
 187
 188         status = fpga_boot(dst, len);
 189         if (status != 0) {
 190                 printf("\nFPGA: Booting failed ");
 191                 switch (status) {
 192                 case ERROR_FPGA_PRG_INIT_LOW:
 193                         printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
 194                         break;
 195                 case ERROR_FPGA_PRG_INIT_HIGH:
 196                         printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
 197                         break;
 198                 case ERROR_FPGA_PRG_DONE:
 199                         printf("(Timeout: DONE not high after programming FPGA)\n ");
 200                         break;
 201                 }
 202
 203                 /* display infos on fpgaimage */
 204                 index = 15;
 205                 for (i=0; i<4; i++) {
 206                         len = dst[index];
 207                         printf("FPGA: %s\n", &(dst[index+1]));
 208                         index += len+3;
 209                 }
 210                 putc ('\n');
 211                 /* delayed reboot */
 212                 for (i=20; i>0; i--) {
 213                         printf("Rebooting in %2d seconds \r",i);
 214                         for (index=0;index<1000;index++)
 215                                 udelay(1000);
 216                 }
 217                 putc ('\n');
 218                 do_reset(NULL, 0, 0, NULL);
 219         }
 220
 221         puts("FPGA:  ");
 222
 223         /* display infos on fpgaimage */
 224         index = 15;
 225         for (i=0; i<4; i++) {
 226                 len = dst[index];
 227                 printf("%s ", &(dst[index+1]));
 228                 index += len+3;
 229         }
 230         putc ('\n');
 231
 232         /*
 233          * Reset FPGA via FPGA_DATA pin
 234          */
 235         SET_FPGA(FPGA_PRG | FPGA_CLK);
 236         udelay(1000); /* wait 1ms */
 237         SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 238         udelay(1000); /* wait 1ms */
 239
 240         /*
 241          * Check if magic for pci reconfig is written
 242          */
 243         magic = (unsigned int *)0x00000004;
 244         if (*magic == PCI_RECONFIG_MAGIC) {
 245                 /*
 246                  * Rewrite pci config regs (only after soft-reset with magic set)
 247                  */
 248                 ptr = (unsigned int *)PCI_REGS_ADDR;
 249                 if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
 250                         puts("Restoring PCI Configurations Regs!\n");
 251                         ptr = (unsigned int *)PCI_REGS_ADDR + 1;
 252                         for (i=0; i<0x40; i+=4) {
 253                                 pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
 254                         }
 255                 }
 256                 mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
 257
 258                 *magic = 0;      /* clear pci reconfig magic again */
 259         }
 260
 261         /*
 262          * Decrease PLB latency timeout and reduce priority of the PCI bridge master
 263          */
 264 #define PCI0_BRDGOPT1 0x4a
 265         pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
 266
 267         /*
 268          * Enable fairness and high bus utilization
 269          */
 270         mtdcr(PLB0_ACR, 0x98000000);
 271
 272         free(dst);
 273         return (0);
 274 }
 275
 276
 277 /*
 278  * Check Board Identity:
 279  */
 280 int checkboard (void)
 281 {
 282         char str[64];
 283         int i = getenv_f("serial#", str, sizeof(str));
 284
 285         puts ("Board: ");
 286
 287         if (i == -1) {
 288                 puts ("### No HW ID - assuming PCI405");
 289         } else {
 290                 puts (str);
 291         }
 292
 293         gd->board_type = board_revision();
 294         printf(" (Rev 1.%ld", gd->board_type);
 295
 296         if (gd->board_type >= 2) {
 297                 unsigned long CPC0_CR0Reg;
 298                 unsigned long value;
 299
 300                 /*
 301                  * Setup GPIO pins (Trace/GPIO1 to GPIO)
 302                  */
 303                 CPC0_CR0Reg = mfdcr(CPC0_CR0);
 304                 mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000);
 305                 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
 306                 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
 307                 udelay(1000);                   /* wait some time before reading input */
 308                 value = in_be32((void*)GPIO0_IR) & 0x40000000;       /* get config bits */
 309                 if (value) {
 310                         puts(", 33 MHz PCI");
 311                 } else {
 312                         puts(", 66 MHz PCI");
 313                 }
 314         }
 315
 316         puts(")\n");
 317
 318         return 0;
 319 }
 320
 321 /* ------------------------------------------------------------------------- */
 322 #define UART1_MCR 0xef600404
 323 int wpeeprom(int wp)
 324 {
 325         int wp_state = wp;
 326
 327         if (wp == 1) {
 328                 out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02);
 329         } else if (wp == 0) {
 330                 out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02);
 331         } else {
 332                 if (in_8((void *)UART1_MCR) & 0x02) {
 333                         wp_state = 0;
 334                 } else {
 335                         wp_state = 1;
 336                 }
 337         }
 338         return wp_state;
 339 }
 340
 341 int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 342 {
 343         int wp = -1;
 344         if (argc >= 2) {
 345                 if (argv[1][0] == '1') {
 346                         wp = 1;
 347                 } else if (argv[1][0] == '0') {
 348                         wp = 0;
 349                 }
 350         }
 351
 352         wp = wpeeprom(wp);
 353         printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
 354         return 0;
 355 }
 356
 357 U_BOOT_CMD(
 358         wpeeprom,       2,      1,      do_wpeeprom,
 359         "Check/Enable/Disable I2C EEPROM write protection",
 360         "wpeeprom\n"
 361         "    - check I2C EEPROM write protection state\n"
 362         "wpeeprom 1\n"
 363         "    - enable I2C EEPROM write protection\n"
 364         "wpeeprom 0\n"
 365         "    - disable I2C EEPROM write protection"
 366 );