board/esd/plu405/plu405.c

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <asm/io.h>
  27 #include <command.h>
  28 #include <malloc.h>
  29 #include <sja1000.h>
  30
  31 #undef FPGA_DEBUG
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
  36 extern void lxt971_no_sleep(void);
  37
  38 /* fpga configuration data - gzip compressed and generated by bin2c */
  39 const unsigned char fpgadata[] =
  40 {
  41 #include "fpgadata.c"
  42 };
  43
  44 /*
  45  * include common fpga code (for esd boards)
  46  */
  47 #include "../common/fpga.c"
  48
  49 /*
  50  * generate a short spike on the CAN tx line
  51  * to bring the couplers in sync
  52  */
  53 void init_coupler(u32 addr)
  54 {
  55         struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
  56
  57         /* reset */
  58         out_8(&ctrl->cr, CR_RR);
  59
  60         /* dominant */
  61         out_8(&ctrl->btr0, 0x00); /* btr setup is required */
  62         out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
  63         out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
  64               OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
  65         out_8(&ctrl->cr, 0x00);
  66
  67         /* delay */
  68         in_8(&ctrl->cr);
  69         in_8(&ctrl->cr);
  70         in_8(&ctrl->cr);
  71         in_8(&ctrl->cr);
  72
  73         /* reset */
  74         out_8(&ctrl->cr, CR_RR);
  75 }
  76
  77 int board_early_init_f(void)
  78 {
  79         /*
  80          * IRQ 0-15  405GP internally generated; active high; level sensitive
  81          * IRQ 16    405GP internally generated; active low; level sensitive
  82          * IRQ 17-24 RESERVED
  83          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
  84          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
  85          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
  86          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
  87          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
  88          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
  89          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
  90          */
  91         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
  92         mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
  93         mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
  94         mtdcr(UIC0PR, 0xFFFFFF99);       /* set int polarities */
  95         mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
  96         mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest prio */
  97         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
  98
  99         /*
 100          * EBC Configuration Register: set ready timeout to
 101          * 512 ebc-clks -> ca. 15 us
 102          */
 103         mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
 104
 105         return 0;
 106 }
 107
 108 int misc_init_r(void)
 109 {
 110         unsigned char *dst;
 111         unsigned char fctr;
 112         ulong len = sizeof(fpgadata);
 113         int status;
 114         int index;
 115         int i;
 116
 117         /* adjust flash start and offset */
 118         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 119         gd->bd->bi_flashoffset = 0;
 120
 121         dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
 122         if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
 123                    (uchar *)fpgadata, &len) != 0) {
 124                 printf("GUNZIP ERROR - must RESET board to recover\n");
 125                 do_reset(NULL, 0, 0, NULL);
 126         }
 127
 128         status = fpga_boot(dst, len);
 129         if (status != 0) {
 130                 printf("\nFPGA: Booting failed ");
 131                 switch (status) {
 132                 case ERROR_FPGA_PRG_INIT_LOW:
 133                         printf("(Timeout: INIT not low "
 134                                "after asserting PROGRAM*)\n");
 135                         break;
 136                 case ERROR_FPGA_PRG_INIT_HIGH:
 137                         printf("(Timeout: INIT not high "
 138                                "after deasserting PROGRAM*)\n");
 139                         break;
 140                 case ERROR_FPGA_PRG_DONE:
 141                         printf("(Timeout: DONE not high "
 142                                "after programming FPGA)\n");
 143                         break;
 144                 }
 145
 146                 /* display infos on fpgaimage */
 147                 index = 15;
 148                 for (i=0; i<4; i++) {
 149                         len = dst[index];
 150                         printf("FPGA: %s\n", &(dst[index+1]));
 151                         index += len+3;
 152                 }
 153                 putc ('\n');
 154                 /* delayed reboot */
 155                 for (i=20; i>0; i--) {
 156                         printf("Rebooting in %2d seconds \r",i);
 157                         for (index=0;index<1000;index++)
 158                                 udelay(1000);
 159                 }
 160                 putc('\n');
 161                 do_reset(NULL, 0, 0, NULL);
 162         }
 163
 164         puts("FPGA:  ");
 165
 166         /* display infos on fpgaimage */
 167         index = 15;
 168         for (i=0; i<4; i++) {
 169                 len = dst[index];
 170                 printf("%s ", &(dst[index+1]));
 171                 index += len+3;
 172         }
 173         putc('\n');
 174
 175         free(dst);
 176
 177         /*
 178          * Reset FPGA via FPGA_DATA pin
 179          */
 180         SET_FPGA(FPGA_PRG | FPGA_CLK);
 181         udelay(1000); /* wait 1ms */
 182         SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 183         udelay(1000); /* wait 1ms */
 184
 185         /*
 186          * Reset external DUARTs
 187          */
 188         out_be32((void*)GPIO0_OR,
 189                  in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
 190         udelay(10);
 191         out_be32((void*)GPIO0_OR,
 192                  in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
 193         udelay(1000);
 194
 195         /*
 196          * Set NAND-FLASH GPIO signals to default
 197          */
 198         out_be32((void*)GPIO0_OR,
 199                  in_be32((void*)GPIO0_OR) &
 200                  ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
 201         out_be32((void*)GPIO0_OR,
 202                  in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
 203
 204         /*
 205          * Setup EEPROM write protection
 206          */
 207         out_be32((void*)GPIO0_OR,
 208                  in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 209         out_be32((void*)GPIO0_TCR,
 210                  in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
 211
 212         /*
 213          * Enable interrupts in exar duart mcr[3]
 214          */
 215         out_8((void *)DUART0_BA + 4, 0x08);
 216         out_8((void *)DUART1_BA + 4, 0x08);
 217
 218         /*
 219          * Enable auto RS485 mode in 2nd external uart
 220          */
 221         out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
 222         fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
 223         fctr |= 0x08;                       /* enable RS485 mode */
 224         out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
 225         out_8((void *)DUART1_BA + 3, 0);    /* write LCR */
 226
 227         /*
 228          * Init magnetic couplers
 229          */
 230         if (!getenv("noinitcoupler")) {
 231                 init_coupler(CAN0_BA);
 232                 init_coupler(CAN1_BA);
 233         }
 234         return 0;
 235 }
 236
 237 /*
 238  * Check Board Identity:
 239  */
 240 int checkboard(void)
 241 {
 242         char str[64];
 243         int i = getenv_r("serial#", str, sizeof(str));
 244
 245         puts("Board: ");
 246
 247         if (i == -1)
 248                 puts("### No HW ID - assuming PLU405");
 249         else
 250                 puts(str);
 251
 252         putc('\n');
 253         return 0;
 254 }
 255
 256 #ifdef CONFIG_IDE_RESET
 257 #define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
 258 void ide_set_reset(int on)
 259 {
 260         /*
 261          * Assert or deassert CompactFlash Reset Pin
 262          */
 263         if (on) {               /* assert RESET */
 264                 out_be16((void *)FPGA_CTRL,
 265                          in_be16((void *)FPGA_CTRL) &
 266                          ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
 267         } else {                /* release RESET */
 268                 out_be16((void *)FPGA_CTRL,
 269                          in_be16((void *)FPGA_CTRL) |
 270                          CONFIG_SYS_FPGA_CTRL_CF_RESET);
 271         }
 272 }
 273 #endif /* CONFIG_IDE_RESET */
 274
 275 void reset_phy(void)
 276 {
 277 #ifdef CONFIG_LXT971_NO_SLEEP
 278
 279         /*
 280          * Disable sleep mode in LXT971
 281          */
 282         lxt971_no_sleep();
 283 #endif
 284 }
 285
 286 #if defined(CONFIG_SYS_EEPROM_WREN)
 287 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
 288  *             <state> -1: deliver current state
 289  *                      0: disable write
 290  *                      1: enable write
 291  *  Returns:           -1: wrong device address
 292  *                      0: dis-/en- able done
 293  *                    0/1: current state if <state> was -1.
 294  */
 295 int eeprom_write_enable(unsigned dev_addr, int state)
 296 {
 297         if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 298                 return -1;
 299         } else {
 300                 switch (state) {
 301                 case 1:
 302                         /* Enable write access, clear bit GPIO0. */
 303                         out_be32((void*)GPIO0_OR,
 304                                  in_be32((void*)GPIO0_OR) &
 305                                  ~CONFIG_SYS_EEPROM_WP);
 306                         state = 0;
 307                         break;
 308                 case 0:
 309                         /* Disable write access, set bit GPIO0. */
 310                         out_be32((void*)GPIO0_OR,
 311                                  in_be32((void*)GPIO0_OR) |
 312                                  CONFIG_SYS_EEPROM_WP);
 313                         state = 0;
 314                         break;
 315                 default:
 316                         /* Read current status back. */
 317                         state = ((in_be32((void*)GPIO0_OR) &
 318                                        CONFIG_SYS_EEPROM_WP) == 0);
 319                         break;
 320                 }
 321         }
 322         return state;
 323 }
 324
 325 int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 326 {
 327         int query = argc == 1;
 328         int state = 0;
 329
 330         if (query) {
 331                 /* Query write access state. */
 332                 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 333                 if (state < 0) {
 334                         puts("Query of write access state failed.\n");
 335                 } else {
 336                         printf("Write access for device 0x%0x is %sabled.\n",
 337                                CONFIG_SYS_I2C_EEPROM_ADDR,
 338                                state ? "en" : "dis");
 339                         state = 0;
 340                 }
 341         } else {
 342                 if (argv[1][0] == '0') {
 343                         /* Disable write access. */
 344                         state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
 345                                                     0);
 346                 } else {
 347                         /* Enable write access. */
 348                         state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
 349                                                     1);
 350                 }
 351                 if (state < 0)
 352                         puts("Setup of write access state failed.\n");
 353         }
 354
 355         return state;
 356 }
 357
 358 U_BOOT_CMD(eepwren,     2,      0,      do_eep_wren,
 359         "Enable / disable / query EEPROM write access",
 360         ""
 361 );
 362 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */