board/esd/pmc405/pmc405.c

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2005
   6  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <asm/processor.h>
  29 #include <command.h>
  30 #include <malloc.h>
  31
  32
  33 extern void lxt971_no_sleep(void);
  34
  35
  36 /* fpga configuration data - not compressed, generated by bin2c */
  37 const unsigned char fpgadata[] =
  38 {
  39 #include "fpgadata.c"
  40 };
  41 int filesize = sizeof(fpgadata);
  42
  43
  44 int board_early_init_f (void)
  45 {
  46         /*
  47          * IRQ 0-15  405GP internally generated; active high; level sensitive
  48          * IRQ 16    405GP internally generated; active low; level sensitive
  49          * IRQ 17-24 RESERVED
  50          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
  51          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
  52          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
  53          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
  54          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
  55          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
  56          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
  57          */
  58         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  59         mtdcr(uicer, 0x00000000);       /* disable all ints */
  60         mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
  61         mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
  62         mtdcr(uictr, 0x10000000);       /* set int trigger levels */
  63         mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
  64         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  65
  66         /*
  67          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
  68          */
  69         mtebc (epcr, 0xa8400000);
  70
  71         /*
  72          * Setup GPIO pins
  73          */
  74
  75         mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_FPGA_INIT | \
  76                                         CFG_FPGA_DONE | \
  77                                         CFG_XEREADY | \
  78                                         CFG_NONMONARCH | \
  79                                         CFG_REV1_2) << 5));
  80
  81         if (!(in32(GPIO0_IR) & CFG_REV1_2)) {
  82                 /* rev 1.2 boards */
  83                 mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_INTA_FAKE | \
  84                                                 CFG_SELF_RST) << 5));
  85         }
  86
  87         out32(GPIO0_OR, 0);
  88         out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA | CFG_XEREADY); /* setup for output */
  89
  90         /* - check if rev1_2 is low, then:
  91          * - set/reset CFG_INTA_FAKE/CFG_SELF_RST in TCR to assert INTA# or SELFRST#
  92          */
  93
  94         return 0;
  95 }
  96
  97
  98 /* ------------------------------------------------------------------------- */
  99
 100
 101 int misc_init_r (void)
 102 {
 103         DECLARE_GLOBAL_DATA_PTR;
 104
 105         /* adjust flash start and offset */
 106         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 107         gd->bd->bi_flashoffset = 0;
 108
 109         out32(GPIO0_OR, in32(GPIO0_OR) | CFG_XEREADY); /* deassert EREADY# */
 110         return (0);
 111 }
 112
 113 ushort pmc405_pci_subsys_deviceid(void)
 114 {
 115         ulong val;
 116         val = in32(GPIO0_IR);
 117         if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
 118                 if (val & CFG_NONMONARCH) { /* monarch# signal */
 119                         return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
 120                 }
 121                 return CFG_PCI_SUBSYS_DEVICEID_MONARCH;
 122         }
 123         return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
 124 }
 125
 126 /*
 127  * Check Board Identity:
 128  */
 129 int checkboard (void)
 130 {
 131         ulong val;
 132
 133         char str[64];
 134         int i = getenv_r ("serial#", str, sizeof(str));
 135
 136         puts ("Board: ");
 137
 138         if (i == -1) {
 139                 puts ("### No HW ID - assuming PMC405");
 140         } else {
 141                 puts(str);
 142         }
 143
 144         val = in32(GPIO0_IR);
 145         if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
 146                 puts(" rev1.2 (");
 147                 if (val & CFG_NONMONARCH) { /* monarch# signal */
 148                         puts("non-");
 149                 }
 150                 puts("monarch)");
 151         } else {
 152                 puts(" <=rev1.1");
 153         }
 154
 155         putc ('\n');
 156
 157         return 0;
 158 }
 159
 160 /* ------------------------------------------------------------------------- */
 161
 162 long int initdram (int board_type)
 163 {
 164         unsigned long val;
 165
 166         mtdcr(memcfga, mem_mb0cf);
 167         val = mfdcr(memcfgd);
 168
 169 #if 0
 170         printf("\nmb0cf=%x\n", val); /* test-only */
 171         printf("strap=%x\n", mfdcr(strap)); /* test-only */
 172 #endif
 173
 174         return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 175 }
 176
 177
 178 /* ------------------------------------------------------------------------- */
 179 void reset_phy(void)
 180 {
 181 #ifdef CONFIG_LXT971_NO_SLEEP
 182
 183         /*
 184          * Disable sleep mode in LXT971
 185          */
 186         lxt971_no_sleep();
 187 #endif
 188 }
 189
 190
 191 int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 192 {
 193         ulong addr;
 194         volatile uchar *ptr;
 195         volatile uchar val;
 196         int i;
 197
 198         addr = simple_strtol (argv[1], NULL, 16) + 0x16;
 199
 200         i = 0;
 201         for (;;) {
 202                 ptr = (uchar *)addr;
 203                 for (i=0; i<8; i++) {
 204                         *ptr = i;
 205                         val = *ptr;
 206
 207                         if (val != i) {
 208                                 printf("ERROR: addr=%p write=0x%02X, read=0x%02X\n", ptr, i, val);
 209                                 return 0;
 210                         }
 211
 212                         /* Abort if ctrl-c was pressed */
 213                         if (ctrlc()) {
 214                                 puts("\nAbort\n");
 215                                 return 0;
 216                         }
 217
 218                         ptr++;
 219                 }
 220         }
 221
 222         return 0;
 223 }
 224 U_BOOT_CMD(
 225         cantest,        3,      1,      do_cantest,
 226         "cantest - Test CAN controller",
 227         NULL
 228         );