board/esd/pmc405de/pmc405de.c

   1 /*
   2  * (C) Copyright 2009
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <console.h>
  10 #include <libfdt.h>
  11 #include <fdt_support.h>
  12 #include <asm/processor.h>
  13 #include <asm/io.h>
  14 #include <asm/ppc4xx-gpio.h>
  15 #include <asm/4xx_pci.h>
  16 #include <command.h>
  17 #include <malloc.h>
  18
  19 /*
  20  * PMC405-DE cpld registers
  21  * - all registers are 8 bit
  22  * - all registers are on 32 bit addesses
  23  */
  24 struct pmc405de_cpld {
  25         /* cpld design version */
  26         u8 version;
  27         u8 reserved0[3];
  28
  29         /* misc. status lines */
  30         u8 status;
  31         u8 reserved1[3];
  32
  33         /*
  34          * gated control flags
  35          * gate bit(s) must be written with '1' to
  36          * access control flag
  37          */
  38         u8 control;
  39         u8 reserved2[3];
  40 };
  41
  42 #define CPLD_VERSION_MASK               0x0f
  43 #define CPLD_CONTROL_POSTLED_N          0x01
  44 #define CPLD_CONTROL_POSTLED_GATE       0x02
  45 #define CPLD_CONTROL_RESETOUT_N         0x40
  46 #define CPLD_CONTROL_RESETOUT_N_GATE    0x80
  47
  48 DECLARE_GLOBAL_DATA_PTR;
  49
  50 extern void __ft_board_setup(void *blob, bd_t *bd);
  51 extern void pll_write(u32 a, u32 b);
  52
  53 static int wait_for_pci_ready_done;
  54
  55 static int is_monarch(void);
  56 static int pci_is_66mhz(void);
  57 static int board_revision(void);
  58 static int cpld_revision(void);
  59 static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div);
  60
  61 int board_early_init_f(void)
  62 {
  63         u32 pllmr0, pllmr1;
  64
  65         /*
  66          * check M66EN and patch PLB:PCI divider for 66MHz PCI
  67          *
  68          * fCPU==333MHz && fPCI==66MHz (PLBDiv==3 && M66EN==1): PLB/PCI=1
  69          * fCPU==333MHz && fPCI==33MHz (PLBDiv==3 && M66EN==0): PLB/PCI=2
  70          * fCPU==133|266MHz && fPCI==66MHz (PLBDiv==1|2 && M66EN==1): PLB/PCI=2
  71          * fCPU==133|266MHz && fPCI==33MHz (PLBDiv==1|2 && M66EN==0): PLB/PCI=3
  72          *
  73          * calling upd_plb_pci_div() may end in calling pll_write() which will
  74          * do a chip reset and never return.
  75          */
  76         pllmr0 = mfdcr(CPC0_PLLMR0);
  77         pllmr1 = mfdcr(CPC0_PLLMR1);
  78
  79         if ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) == PLLMR0_CPU_PLB_DIV_3) {
  80                 /* fCPU=333MHz, fPLB=111MHz */
  81                 if (pci_is_66mhz())
  82                         upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_1);
  83                 else
  84                         upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
  85         } else {
  86                 /* fCPU=133|266MHz, fPLB=133MHz */
  87                 if (pci_is_66mhz())
  88                         upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
  89                 else
  90                         upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_3);
  91         }
  92
  93         /*
  94          * IRQ 25 (EXT IRQ 0) PCI-INTA#; active low; level sensitive
  95          * IRQ 26 (EXT IRQ 1) PCI-INTB#; active low; level sensitive
  96          * IRQ 27 (EXT IRQ 2) PCI-INTC#; active low; level sensitive
  97          * IRQ 28 (EXT IRQ 3) PCI-INTD#; active low; level sensitive
  98          * IRQ 29 (EXT IRQ 4) ETH0-PHY-IRQ#; active low; level sensitive
  99          * IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive
 100          * IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive
 101          */
 102         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 103         mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
 104         mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
 105         mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
 106         mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
 107         mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0, INT0 highest prio */
 108         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 109
 110         /*
 111          * EBC Configuration Register:
 112          * - set ready timeout to 512 ebc-clks -> ca. 15 us
 113          * - EBC lines are always driven
 114          */
 115         mtebc(EBC0_CFG, 0xa8400000);
 116
 117         return 0;
 118 }
 119
 120 static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div)
 121 {
 122         if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != div)
 123                 pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | div, pllmr1);
 124 }
 125
 126 int misc_init_r(void)
 127 {
 128         int i;
 129         struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
 130         struct pmc405de_cpld *cpld =
 131                 (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
 132
 133         if (!is_monarch()) {
 134                 /* PCI configuration done: release EREADY */
 135                 setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EREADY);
 136                 setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_EREADY);
 137         }
 138
 139         /* turn off POST LED */
 140         out_8(&cpld->control,
 141               CPLD_CONTROL_POSTLED_N | CPLD_CONTROL_POSTLED_GATE);
 142
 143         /* turn on LEDs: RUN, A, B */
 144         clrbits_be32(&gpio0->or,
 145                      CONFIG_SYS_GPIO_LEDRUN_N |
 146                      CONFIG_SYS_GPIO_LEDA_N |
 147                      CONFIG_SYS_GPIO_LEDB_N);
 148
 149         for (i=0; i < 200; i++)
 150                 udelay(1000);
 151
 152         /* turn off LEDs: A, B */
 153         setbits_be32(&gpio0->or,
 154                      CONFIG_SYS_GPIO_LEDA_N |
 155                      CONFIG_SYS_GPIO_LEDB_N);
 156
 157         return (0);
 158 }
 159
 160 static int is_monarch(void)
 161 {
 162         struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
 163         return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_MONARCH_N) == 0;
 164 }
 165
 166 static int pci_is_66mhz(void)
 167 {
 168         struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
 169         return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_M66EN);
 170 }
 171
 172 static int board_revision(void)
 173 {
 174         struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
 175         return ((in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_HWREV_MASK) >>
 176                 CONFIG_SYS_GPIO_HWREV_SHIFT);
 177 }
 178
 179 static int cpld_revision(void)
 180 {
 181         struct pmc405de_cpld *cpld =
 182                 (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
 183         return ((in_8(&cpld->version) & CPLD_VERSION_MASK));
 184 }
 185
 186 /*
 187  * Check Board Identity
 188  */
 189 int checkboard(void)
 190 {
 191         puts("Board: esd GmbH - PMC-CPU/405-DE");
 192
 193         gd->board_type = board_revision();
 194         printf(", Rev 1.%ld, ", gd->board_type);
 195
 196         if (!is_monarch())
 197                 puts("non-");
 198
 199         printf("monarch, PCI=%s MHz, PLD-Rev 1.%d\n",
 200                pci_is_66mhz() ? "66" : "33", cpld_revision());
 201
 202         return 0;
 203 }
 204
 205
 206 static void wait_for_pci_ready(void)
 207 {
 208         struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
 209         int i;
 210         char *s = getenv("pcidelay");
 211
 212         /* only wait once */
 213         if (wait_for_pci_ready_done)
 214                 return;
 215
 216         /*
 217          * We have our own handling of the pcidelay variable.
 218          * Using CONFIG_PCI_BOOTDELAY enables pausing for host
 219          * and adapter devices. For adapter devices we do not
 220          * want this.
 221          */
 222         if (s) {
 223                 int ms = simple_strtoul(s, NULL, 10);
 224                 printf("PCI:   Waiting for %d ms\n", ms);
 225                 for (i=0; i<ms; i++)
 226                         udelay(1000);
 227         }
 228
 229         if (!(in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY)) {
 230                 printf("PCI:   Waiting for EREADY (CTRL-C to skip) ... ");
 231                 while (1) {
 232                         if (ctrlc()) {
 233                                 puts("abort\n");
 234                                 break;
 235                         }
 236                         if (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY) {
 237                                 printf("done\n");
 238                                 break;
 239                         }
 240                 }
 241         }
 242
 243         wait_for_pci_ready_done = 1;
 244 }
 245
 246 /*
 247  * Overwrite weak is_pci_host()
 248  *
 249  * This routine is called to determine if a pci scan should be
 250  * performed. With various hardware environments (especially cPCI and
 251  * PPMC) it's insufficient to depend on the state of the arbiter enable
 252  * bit in the strap register, or generic host/adapter assumptions.
 253  *
 254  * Return 0 for adapter mode, non-zero for host (monarch) mode.
 255  */
 256 int is_pci_host(struct pci_controller *hose)
 257 {
 258         char *s;
 259
 260         if (!is_monarch()) {
 261                 /*
 262                  * Overwrite PCI identification when running in
 263                  * non-monarch mode
 264                  * This should be moved into pci_target_init()
 265                  * when it is sometimes available for 405 CPUs
 266                  */
 267                 pci_write_config_word(PCIDEVID_405GP,
 268                                       PCI_SUBSYSTEM_ID,
 269                                       CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
 270                 pci_write_config_word(PCIDEVID_405GP,
 271                                       PCI_CLASS_SUB_CODE,
 272                                       CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
 273         }
 274
 275         s = getenv("pciscan");
 276         if (s == NULL) {
 277                 if (is_monarch()) {
 278                         wait_for_pci_ready();
 279                         return 1;
 280                 } else {
 281                         return 0;
 282                 }
 283         } else {
 284                 if (!strcmp(s, "yes"))
 285                         return 1;
 286         }
 287
 288         return 0;
 289 }
 290
 291 /*
 292  * Overwrite weak pci_pre_init()
 293  *
 294  * The default implementation enables the 405EP
 295  * internal PCI arbiter. We do not want that
 296  * on a PMC module.
 297  */
 298 int pci_pre_init(struct pci_controller *hose)
 299 {
 300         return 1;
 301 }
 302
 303 #ifdef CONFIG_OF_BOARD_SETUP
 304 int ft_board_setup(void *blob, bd_t *bd)
 305 {
 306         int rc;
 307
 308         __ft_board_setup(blob, bd);
 309
 310         /*
 311          * Disable PCI in non-monarch mode.
 312          */
 313         if (!is_monarch()) {
 314                 rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
 315                                           "disabled", sizeof("disabled"), 1);
 316                 if (rc) {
 317                         printf("Unable to update property status in PCI node, "
 318                                "err=%s\n",
 319                                fdt_strerror(rc));
 320                 }
 321         }
 322
 323         return 0;
 324 }
 325 #endif /* CONFIG_OF_BOARD_SETUP */
 326
 327 #if defined(CONFIG_SYS_EEPROM_WREN)
 328 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
 329  *         <state>     -1: deliver current state
 330  *                      0: disable write
 331  *                      1: enable write
 332  * Returns:            -1: wrong device address
 333  *                      0: dis-/en- able done
 334  *                    0/1: current state if <state> was -1.
 335  */
 336 int eeprom_write_enable(unsigned dev_addr, int state)
 337 {
 338         struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
 339
 340         if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 341                 return -1;
 342         } else {
 343                 switch (state) {
 344                 case 1:
 345                         /* Enable write access, clear bit GPIO0. */
 346                         clrbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
 347                         state = 0;
 348                         break;
 349                 case 0:
 350                         /* Disable write access, set bit GPIO0. */
 351                         setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
 352                         state = 0;
 353                         break;
 354                 default:
 355                         /* Read current status back. */
 356                         state = (0 == (in_be32(&gpio0->or) &
 357                                        CONFIG_SYS_GPIO_EEPROM_WP));
 358                         break;
 359                 }
 360         }
 361         return state;
 362 }
 363
 364 int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 365 {
 366         int query = argc == 1;
 367         int state = 0;
 368
 369         if (query) {
 370                 /* Query write access state. */
 371                 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 1);
 372                 if (state < 0) {
 373                         puts("Query of write access state failed.\n");
 374                 } else {
 375                         printf("Write access for device 0x%0x is %sabled.\n",
 376                                 CONFIG_SYS_I2C_EEPROM_ADDR,
 377                                 state ? "en" : "dis");
 378                         state = 0;
 379                 }
 380         } else {
 381                 if ('0' == argv[1][0]) {
 382                         /* Disable write access. */
 383                         state = eeprom_write_enable(
 384                                 CONFIG_SYS_I2C_EEPROM_ADDR, 0);
 385                 } else {
 386                         /* Enable write access. */
 387                         state = eeprom_write_enable(
 388                                 CONFIG_SYS_I2C_EEPROM_ADDR, 1);
 389                 }
 390                 if (state < 0)
 391                         puts ("Setup of write access state failed.\n");
 392         }
 393
 394         return state;
 395 }
 396
 397 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
 398         "Enable / disable / query EEPROM write access",
 399         ""
 400 );
 401 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
 402
 403 #if defined(CONFIG_PRAM)
 404 #include <environment.h>
 405
 406 int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 407 {
 408         u32 pram, nextbase, base;
 409         char *v;
 410         u32 param;
 411         ulong *lptr;
 412
 413         v = getenv("pram");
 414         if (v)
 415                 pram = simple_strtoul(v, NULL, 10);
 416         else {
 417                 printf("Error: pram undefined. Please define pram in KiB\n");
 418                 return 1;
 419         }
 420
 421         base = gd->bd->bi_memsize;
 422 #if defined(CONFIG_LOGBUFFER)
 423         base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
 424 #endif
 425         /*
 426          * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MM_TOP_HIDE
 427          */
 428         param = base - (pram << 10);
 429         printf("PARAM: @%08x\n", param);
 430         debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base);
 431
 432         /* clear entire PA ram */
 433         memset((void*)param, 0, (pram << 10));
 434
 435         /* reserve 4k for pointer field */
 436         nextbase = base - 4096;
 437         lptr = (ulong*)(base);
 438
 439         /*
 440          * *(--lptr) = item_size;
 441          * *(--lptr) = base - item_base = distance from field top;
 442          */
 443
 444         /* env is first (4k aligned) */
 445         nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
 446         memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE);
 447         *(--lptr) = CONFIG_ENV_SIZE;     /* size */
 448         *(--lptr) = base - nextbase;  /* offset | type=0 */
 449
 450         /* free section */
 451         *(--lptr) = nextbase - param; /* size */
 452         *(--lptr) = (base - param) | 126; /* offset | type=126 */
 453
 454         /* terminate pointer field */
 455         *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
 456         *(--lptr) = 0;                /* offset=0 -> terminator */
 457         return 0;
 458 }
 459 U_BOOT_CMD(
 460         painit, 1,      1,      do_painit,
 461         "prepare PciAccess system",
 462         ""
 463 );
 464 #endif /* CONFIG_PRAM */
 465
 466 int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 467 {
 468         struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
 469         setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_SELFRST_N);
 470         return 0;
 471 }
 472 U_BOOT_CMD(
 473         selfreset,      1,      1,      do_selfreset,
 474         "assert self-reset# signal",
 475         ""
 476 );
 477
 478 int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 479 {
 480         struct pmc405de_cpld *cpld =
 481                 (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
 482
 483         if (argc > 1) {
 484                 if (argv[1][0] == '0') {
 485                         /* assert */
 486                         printf("PMC-RESETOUT# asserted\n");
 487                         out_8(&cpld->control,
 488                               CPLD_CONTROL_RESETOUT_N_GATE);
 489                 } else {
 490                         /* deassert */
 491                         printf("PMC-RESETOUT# deasserted\n");
 492                         out_8(&cpld->control,
 493                               CPLD_CONTROL_RESETOUT_N |
 494                               CPLD_CONTROL_RESETOUT_N_GATE);
 495                 }
 496         } else {
 497                 printf("PMC-RESETOUT# is %s\n",
 498                        (in_8(&cpld->control) & CPLD_CONTROL_RESETOUT_N) ?
 499                        "inactive" : "active");
 500         }
 501         return 0;
 502 }
 503 U_BOOT_CMD(
 504         resetout,       2,      1,      do_resetout,
 505         "assert PMC-RESETOUT# signal",
 506         ""
 507 );