2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
30 /* ------------------------------------------------------------------------- */
36 extern int do_reset (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[]);
37 extern void lxt971_no_sleep(void);
39 /* fpga configuration data - gzip compressed and generated by bin2c */
40 const unsigned char fpgadata
[] =
46 * include common fpga code (for esd boards)
48 #include "../common/fpga.c"
52 int gunzip(void *, int, unsigned char *, unsigned long *);
55 /* logo bitmap data - gzip compressed and generated by bin2c */
56 unsigned char logo_bmp_320
[] =
58 #include "logo_320_240_4bpp.c"
61 unsigned char logo_bmp_640
[] =
63 #include "logo_640_480_24bpp.c"
68 * include common lcd code (for esd boards)
70 #include "../common/lcd.c"
72 #include "../common/s1d13704_320_240_4bpp.h"
73 #include "../common/s1d13806_320_240_4bpp.h"
74 #include "../common/s1d13806_640_480_16bpp.h"
77 int board_early_init_f (void)
80 * IRQ 0-15 405GP internally generated; active high; level sensitive
81 * IRQ 16 405GP internally generated; active low; level sensitive
83 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
84 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
85 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
86 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
87 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
88 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
89 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
91 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
92 mtdcr(uicer
, 0x00000000); /* disable all ints */
93 mtdcr(uiccr
, 0x00000000); /* set all to be non-critical*/
94 mtdcr(uicpr
, 0xFFFFFFB5); /* set int polarities */
95 mtdcr(uictr
, 0x10000000); /* set int trigger levels */
96 mtdcr(uicvcr
, 0x00000001); /* set vect base=0,INT0 highest priority*/
97 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
100 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
102 mtebc (epcr
, 0xa8400000); /* ebc always driven */
107 int misc_init_r (void)
109 unsigned char *duart0_mcr
= (unsigned char *)((ulong
)DUART0_BA
+ 4);
110 unsigned char *duart1_mcr
= (unsigned char *)((ulong
)DUART1_BA
+ 4);
111 unsigned short *lcd_contrast
=
112 (unsigned short *)((ulong
)CONFIG_SYS_FPGA_BASE_ADDR
+ CONFIG_SYS_FPGA_CTRL
+ 4);
113 unsigned short *lcd_backlight
=
114 (unsigned short *)((ulong
)CONFIG_SYS_FPGA_BASE_ADDR
+ CONFIG_SYS_FPGA_CTRL
+ 6);
116 ulong len
= sizeof(fpgadata
);
122 dst
= malloc(CONFIG_SYS_FPGA_MAX_SIZE
);
123 if (gunzip (dst
, CONFIG_SYS_FPGA_MAX_SIZE
, (uchar
*)fpgadata
, &len
) != 0) {
124 printf ("GUNZIP ERROR - must RESET board to recover\n");
125 do_reset (NULL
, 0, 0, NULL
);
128 status
= fpga_boot(dst
, len
);
130 printf("\nFPGA: Booting failed ");
132 case ERROR_FPGA_PRG_INIT_LOW
:
133 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
135 case ERROR_FPGA_PRG_INIT_HIGH
:
136 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
138 case ERROR_FPGA_PRG_DONE
:
139 printf("(Timeout: DONE not high after programming FPGA)\n ");
143 /* display infos on fpgaimage */
145 for (i
=0; i
<4; i
++) {
147 printf("FPGA: %s\n", &(dst
[index
+1]));
152 for (i
=20; i
>0; i
--) {
153 printf("Rebooting in %2d seconds \r",i
);
154 for (index
=0;index
<1000;index
++)
158 do_reset(NULL
, 0, 0, NULL
);
163 /* display infos on fpgaimage */
165 for (i
=0; i
<4; i
++) {
167 printf("%s ", &(dst
[index
+1]));
175 * Reset FPGA via FPGA_INIT pin
177 out_be32((void*)GPIO0_TCR
, in_be32((void*)GPIO0_TCR
) | FPGA_INIT
); /* setup FPGA_INIT as output */
178 out_be32((void*)GPIO0_OR
, in_be32((void*)GPIO0_OR
) & ~FPGA_INIT
); /* reset low */
179 udelay(1000); /* wait 1ms */
180 out_be32((void*)GPIO0_OR
, in_be32((void*)GPIO0_OR
) | FPGA_INIT
); /* reset high */
181 udelay(1000); /* wait 1ms */
184 * Reset external DUARTs
186 out_be32((void*)GPIO0_OR
, in_be32((void*)GPIO0_OR
) | CONFIG_SYS_DUART_RST
); /* set reset to high */
187 udelay(10); /* wait 10us */
188 out_be32((void*)GPIO0_OR
, in_be32((void*)GPIO0_OR
) & ~CONFIG_SYS_DUART_RST
); /* set reset to low */
189 udelay(1000); /* wait 1ms */
192 * Set NAND-FLASH GPIO signals to default
194 out_be32((void*)GPIO0_OR
, in_be32((void*)GPIO0_OR
) & ~(CONFIG_SYS_NAND_CLE
| CONFIG_SYS_NAND_ALE
));
195 out_be32((void*)GPIO0_OR
, in_be32((void*)GPIO0_OR
) | CONFIG_SYS_NAND_CE
);
198 * Setup EEPROM write protection
200 out_be32((void*)GPIO0_OR
, in_be32((void*)GPIO0_OR
) | CONFIG_SYS_EEPROM_WP
);
201 out_be32((void*)GPIO0_TCR
, in_be32((void*)GPIO0_TCR
) | CONFIG_SYS_EEPROM_WP
);
204 * Enable interrupts in exar duart mcr[3]
206 out_8(duart0_mcr
, 0x08);
207 out_8(duart1_mcr
, 0x08);
210 * Init lcd interface and display logo
212 str
= getenv("bd_type");
213 if (strcmp(str
, "voh405_bw") == 0) {
215 lcd_init((uchar
*)CONFIG_SYS_LCD_SMALL_REG
, (uchar
*)CONFIG_SYS_LCD_SMALL_MEM
,
216 regs_13704_320_240_4bpp
,
217 sizeof(regs_13704_320_240_4bpp
)/sizeof(regs_13704_320_240_4bpp
[0]),
218 logo_bmp_320
, sizeof(logo_bmp_320
));
219 } else if (strcmp(str
, "voh405_bwbw") == 0) {
221 lcd_init((uchar
*)CONFIG_SYS_LCD_SMALL_REG
, (uchar
*)CONFIG_SYS_LCD_SMALL_MEM
,
222 regs_13704_320_240_4bpp
,
223 sizeof(regs_13704_320_240_4bpp
)/sizeof(regs_13704_320_240_4bpp
[0]),
224 logo_bmp_320
, sizeof(logo_bmp_320
));
226 lcd_init((uchar
*)CONFIG_SYS_LCD_BIG_REG
, (uchar
*)CONFIG_SYS_LCD_BIG_MEM
,
227 regs_13806_320_240_4bpp
,
228 sizeof(regs_13806_320_240_4bpp
)/sizeof(regs_13806_320_240_4bpp
[0]),
229 logo_bmp_320
, sizeof(logo_bmp_320
));
230 } else if (strcmp(str
, "voh405_bwc") == 0) {
232 lcd_init((uchar
*)CONFIG_SYS_LCD_SMALL_REG
, (uchar
*)CONFIG_SYS_LCD_SMALL_MEM
,
233 regs_13704_320_240_4bpp
,
234 sizeof(regs_13704_320_240_4bpp
)/sizeof(regs_13704_320_240_4bpp
[0]),
235 logo_bmp_320
, sizeof(logo_bmp_320
));
237 lcd_init((uchar
*)CONFIG_SYS_LCD_BIG_REG
, (uchar
*)CONFIG_SYS_LCD_BIG_MEM
,
238 regs_13806_640_480_16bpp
,
239 sizeof(regs_13806_640_480_16bpp
)/sizeof(regs_13806_640_480_16bpp
[0]),
240 logo_bmp_640
, sizeof(logo_bmp_640
));
242 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str
);
247 * Set invert bit in small lcd controller
249 out_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG
+ 2),
250 in_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG
+ 2)) | 0x01);
253 * Set default contrast voltage on epson vga controller
255 out_be16(lcd_contrast
, 0x4646);
260 out_be16(lcd_backlight
, 0xffff);
263 * Enable external I2C bus
265 out_be32((void*)GPIO0_TCR
, in_be32((void*)GPIO0_TCR
) | CONFIG_SYS_IIC_ON
);
272 * Check Board Identity:
275 int checkboard (void)
278 int i
= getenv_r ("serial#", str
, sizeof(str
));
283 puts ("### No HW ID - assuming VOH405");
288 if (getenv_r("bd_type", str
, sizeof(str
)) != -1) {
289 printf(" (%s)", str
);
291 puts(" (Missing bd_type!)");
299 #ifdef CONFIG_IDE_RESET
300 #define FPGA_MODE (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
301 void ide_set_reset(int on
)
304 * Assert or deassert CompactFlash Reset Pin
306 if (on
) { /* assert RESET */
307 out_be16((void *)FPGA_MODE
,
308 in_be16((void *)FPGA_MODE
) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET
);
309 } else { /* release RESET */
310 out_be16((void *)FPGA_MODE
,
311 in_be16((void *)FPGA_MODE
) | CONFIG_SYS_FPGA_CTRL_CF_RESET
);
314 #endif /* CONFIG_IDE_RESET */
316 #if defined(CONFIG_RESET_PHY_R)
319 #ifdef CONFIG_LXT971_NO_SLEEP
322 * Disable sleep mode in LXT971
329 #if defined(CONFIG_SYS_EEPROM_WREN)
330 /* Input: <dev_addr> I2C address of EEPROM device to enable.
331 * <state> -1: deliver current state
334 * Returns: -1: wrong device address
335 * 0: dis-/en- able done
336 * 0/1: current state if <state> was -1.
338 int eeprom_write_enable (unsigned dev_addr
, int state
)
340 if (CONFIG_SYS_I2C_EEPROM_ADDR
!= dev_addr
) {
345 /* Enable write access, clear bit GPIO0. */
346 out_be32((void*)GPIO0_OR
, in_be32((void*)GPIO0_OR
) & ~CONFIG_SYS_EEPROM_WP
);
350 /* Disable write access, set bit GPIO0. */
351 out_be32((void*)GPIO0_OR
, in_be32((void*)GPIO0_OR
) | CONFIG_SYS_EEPROM_WP
);
355 /* Read current status back. */
356 state
= (0 == (in_be32((void*)GPIO0_OR
) & CONFIG_SYS_EEPROM_WP
));
363 int do_eep_wren (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
365 int query
= argc
== 1;
369 /* Query write access state. */
370 state
= eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR
, -1);
372 puts ("Query of write access state failed.\n");
374 printf ("Write access for device 0x%0x is %sabled.\n",
375 CONFIG_SYS_I2C_EEPROM_ADDR
, state
? "en" : "dis");
379 if ('0' == argv
[1][0]) {
380 /* Disable write access. */
381 state
= eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR
, 0);
383 /* Enable write access. */
384 state
= eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR
, 1);
387 puts ("Setup of write access state failed.\n");
394 U_BOOT_CMD(eepwren
, 2, 0, do_eep_wren
,
395 "Enable / disable / query EEPROM write access",
398 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */