board/espt/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2009 Renesas Solutions Corp.
   3  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   4  *
   5  * board/espt/lowlevel_init.S
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <config.h>
  11 #include <asm/processor.h>
  12 #include <asm/macro.h>
  13
  14         .global lowlevel_init
  15
  16         .text
  17         .align  2
  18
  19 lowlevel_init:
  20
  21         write32 WDTCSR_A, WDTCSR_D
  22
  23         write32 WDTST_A, WDTST_D
  24
  25         write32 WDTBST_A, WDTBST_D
  26
  27         write32 CCR_A, CCR_CACHE_ICI_D
  28
  29         write32 MMUCR_A, MMU_CONTROL_TI_D
  30
  31         write32 MSTPCR0_A, MSTPCR0_D
  32
  33         write32 MSTPCR1_A, MSTPCR1_D
  34
  35         write32 RAMCR_A, RAMCR_D
  36
  37         /*
  38          * Setting infomation from
  39          * original ESPT-GIGA bootloader register
  40          */
  41         write32 MMSEL_A, MMSEL_D
  42
  43         /* dummy */
  44         mov.l   @r1, r2
  45         mov.l   @r1, r2
  46         synco
  47
  48     write32 BCR_A, BCR_D
  49
  50     write32 CS0BCR_A, CS0BCR_D
  51
  52     write32 CS0WCR_A, CS0WCR_D
  53
  54         /*
  55          * DDR-SDRAM setting
  56          */
  57
  58         /* set DDR-SDRAM dummy read */
  59         write32 MMSEL_A, MMSEL_D
  60
  61         write32 MMSEL_A, CS0_A
  62
  63         /* set DDR-SDRAM bus/endian etc */
  64         write32 MIM_U_A, MIM_U_D
  65
  66         write32 MIM_L_A, MIM_L_D0
  67
  68         write32 SDR_L_A, SDR_L_A_D0
  69
  70         write32 STR_L_A, STR_L_A_D0
  71
  72         /* DDR-SDRAM access control */
  73         write32 MIM_L_A, MIM_L_D1
  74
  75         write32 SCR_L_A, SCR_L_A_D0
  76
  77         write32 SCR_L_A, SCR_L_A_D1
  78
  79         write32 EMRS_A, EMRS_D
  80
  81         write32 MRS1_A, MRS1_D
  82
  83         write32 MIM_U_A, MIM_U_D
  84
  85         write32 MIM_L_A, MIM_L_A_D2
  86
  87         write32 SCR_L_A, SCR_L_A_D2
  88
  89         write32 SCR_L_A, SCR_L_A_D2
  90
  91         write32 MRS2_A, MRS2_D
  92
  93         /* wait 200us */
  94         wait_timer REPEAT_R3
  95
  96         /* GPIO setting */
  97         write16 PSEL0_A, PSEL0_D
  98
  99         write16 PSEL1_A, PSEL1_D
 100
 101         write16 PSEL2_A, PSEL2_D
 102
 103         write16 PSEL3_A, PSEL3_D
 104
 105         write16 PSEL4_A, PSEL4_D
 106
 107         write8 PADR_A, PADR_D
 108
 109         write16 PACR_A, PACR_D
 110
 111         write8 PBDR_A, PBDR_D
 112
 113         write16 PBCR_A, PBCR_D
 114
 115         write8 PCDR_A, PCDR_D
 116
 117         write16 PCCR_A, PCCR_D
 118
 119         write8  PDDR_A, PDDR_D
 120
 121         write16 PDCR_A, PDCR_D
 122
 123         write16 PECR_A, PECR_D
 124
 125         write16 PFCR_A, PFCR_D
 126
 127         write16 PGCR_A, PGCR_D
 128
 129         write16 PHCR_A, PHCR_D
 130
 131         write16 PICR_A, PICR_D
 132
 133         write8 PJDR_A, PJDR_D
 134
 135         write16 PJCR_A, PJCR_D
 136
 137         /* wait 50us */
 138         wait_timer REPEAT_R3
 139
 140         write8 PKDR_A, PKDR_D
 141
 142         write16 PKCR_A, PKCR_D
 143
 144         write16 PLCR_A, PLCR_D
 145
 146         write16 PMCR_A, PMCR_D
 147
 148         write16 PNCR_A, PNCR_D
 149
 150         write16 POCR_A, POCR_D
 151
 152
 153         /* ICR0 ,ICR1 */
 154         write32 ICR0_A, ICR0_D
 155
 156         write32 ICR1_A, ICR1_D
 157
 158         /* USB Host */
 159         write32 USB_USBHSC_A, USB_USBHSC_D
 160
 161         write32 CCR_A, CCR_CACHE_D_2
 162
 163         rts
 164         nop
 165
 166         .align  2
 167
 168 /* GPIO Crontrol Register */
 169 PACR_A: .long   0xFFEF0000
 170 PBCR_A: .long   0xFFEF0002
 171 PCCR_A: .long   0xFFEF0004
 172 PDCR_A: .long   0xFFEF0006
 173 PECR_A: .long   0xFFEF0008
 174 PFCR_A: .long   0xFFEF000A
 175 PGCR_A: .long   0xFFEF000C
 176 PHCR_A: .long   0xFFEF000E
 177 PICR_A: .long   0xFFEF0010
 178 PJCR_A: .long   0xFFEF0012
 179 PKCR_A: .long   0xFFEF0014
 180 PLCR_A: .long   0xFFEF0016
 181 PMCR_A: .long   0xFFEF0018
 182 PNCR_A: .long   0xFFEF001A
 183 POCR_A: .long   0xFFEF001C
 184
 185 /* GPIO Data Register */
 186 PADR_A: .long   0xFFEF0020
 187 PBDR_A: .long   0xFFEF0022
 188 PCDR_A: .long   0xFFEF0024
 189 PDDR_A: .long   0xFFEF0026
 190 PJDR_A: .long   0xFFEF0032
 191 PKDR_A: .long   0xFFEF0034
 192
 193 /* GPIO Set data */
 194 PADR_D: .long   0x00000000
 195 PACR_D: .word   0x1400
 196 .align 2
 197 PBDR_D: .long   0x00000000
 198 PBCR_D: .word   0x555A
 199 .align 2
 200 PCDR_D: .long   0x00000000
 201 PCCR_D: .word   0x5555
 202 .align 2
 203 PDDR_D: .long   0x00000000
 204 PDCR_D: .word   0x0155
 205 PECR_D: .word   0x0000
 206 PFCR_D: .word   0x0000
 207 PGCR_D: .word   0x0000
 208 PHCR_D: .word   0x0000
 209 PICR_D: .word   0x0800
 210 PJDR_D: .long   0x00000006
 211 PJCR_D: .word   0x5A57
 212 .align 2
 213 PKDR_D: .long   0x00000000
 214 PKCR_D: .word   0xFFF9
 215 .align 2
 216 PLCR_D: .word   0xC330
 217 PMCR_D: .word   0xFFFF
 218 PNCR_D: .word   0x0242
 219 POCR_D: .word   0x0000
 220
 221 /* Pin Select */
 222 PSEL0_A:        .long   0xFFEF0070
 223 PSEL1_A:        .long   0xFFEF0072
 224 PSEL2_A:        .long   0xFFEF0074
 225 PSEL3_A:        .long   0xFFEF0076
 226 PSEL4_A:        .long   0xFFEF0078
 227 PSEL0_D:        .word   0x0001
 228 PSEL1_D:        .word   0x2400
 229 PSEL2_D:        .word   0x0000
 230 PSEL3_D:        .word   0x2421
 231 PSEL4_D:        .word   0x0000
 232 .align 2
 233
 234 MMSEL_A:        .long   0xFE600020
 235 BCR_A:          .long   0xFF801000
 236 CS0BCR_A:       .long   0xFF802000
 237 CS0WCR_A:       .long   0xFF802008
 238 ICR0_A:         .long   0xFFD00000
 239 ICR1_A:         .long   0xFFD0001C
 240
 241 MMSEL_D:        .long   0xA5A50000
 242 BCR_D:          .long   0x05000000
 243 CS0BCR_D:       .long   0x232306F0
 244 CS0WCR_D:       .long   0x00011104
 245 ICR0_D:         .long   0x80C00000
 246 ICR1_D:         .long   0x00020000
 247
 248 /* RWBT Address */
 249 WDTST_A:        .long   0xFFCC0000
 250 WDTCSR_A:       .long   0xFFCC0004
 251 WDTBST_A:       .long   0xFFCC0008
 252 /* RWBT Data */
 253 WDTST_D:        .long   0x5A000FFF
 254 WDTCSR_D:       .long   0xA5000000
 255 WDTBST_D:       .long   0x55000000
 256
 257 /* Cache Address */
 258 CCR_A:          .long   0xFF00001C
 259 MMUCR_A:        .long   0xFF000010
 260 RAMCR_A:        .long   0xFF000074
 261
 262 /* Cache Data */
 263 CCR_CACHE_ICI_D:.long   0x00000800
 264 CCR_CACHE_D_2:  .long   0x00000103
 265 MMU_CONTROL_TI_D:.long  0x00000004
 266 RAMCR_D:        .long   0x00000200
 267
 268 /* Low power mode control Address */
 269 MSTPCR0_A:      .long   0xFFC80030
 270 MSTPCR1_A:      .long   0xFFC80038
 271 /* Low power mode control Data */
 272 MSTPCR0_D:      .long   0x00000000
 273 MSTPCR1_D:      .long   0x00000000
 274
 275 REPEAT0_R3:     .long   0x00002000
 276 REPEAT_R3:      .long   0x00000200
 277 CS0_A:          .long   0xA8000000
 278
 279 MIM_U_A:        .long   0xFE800008
 280 MIM_L_A:        .long   0xFE80000C
 281 SCR_U_A:        .long   0xFE800010
 282 SCR_L_A:        .long   0xFE800014
 283 STR_U_A:        .long   0xFE800018
 284 STR_L_A:        .long   0xFE80001C
 285 SDR_U_A:        .long   0xFE800030
 286 SDR_L_A:        .long   0xFE800034
 287 EMRS_A:         .long   0xFE902000
 288 MRS1_A:         .long   0xFE900B08
 289 MRS2_A:         .long   0xFE900308
 290
 291 MIM_U_D:        .long   0x00000000
 292 MIM_L_D0:       .long   0x04100008
 293 MIM_L_D1:       .long   0x02EE0009
 294 MIM_L_D2:       .long   0x02EE0209
 295
 296 SDR_L_A_D0:     .long   0x00000300
 297 STR_L_A_D0:     .long   0x00010040
 298 MIM_L_A_D1:     .long   0x04100009
 299 SCR_L_A_D0:     .long   0x00000003
 300 SCR_L_A_D1:     .long   0x00000002
 301 MIM_L_A_D2:     .long   0x04100209
 302 SCR_L_A_D2:     .long   0x00000004
 303
 304 SCR_L_NORMAL:   .long   0x00000000
 305 SCR_L_NOP:              .long   0x00000001
 306 SCR_L_PALL:             .long   0x00000002
 307 SCR_L_CKE_EN:   .long   0x00000003
 308 SCR_L_CBR:              .long   0x00000004
 309
 310 STR_L_D:        .long   0x000F3980
 311 SDR_L_D:        .long   0x00000400
 312 EMRS_D:         .long   0x00000000
 313 MRS1_D:         .long   0x00000000
 314 MRS2_D:         .long   0x00000000
 315
 316 /* USB */
 317 USB_USBHSC_A:   .long   0xFFEC80F0
 318 USB_USBHSC_D:   .long   0x00000000