board/etin/debris/debris.c

   1 /*
   2  * (C) Copyright 2000
   3  * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <mpc824x.h>
  26 #include <pci.h>
  27 #include <i2c.h>
  28
  29 int checkboard (void)
  30 {
  31         /*TODO: Check processor type */
  32
  33         puts (  "Board: Debris "
  34 #ifdef CONFIG_MPC8240
  35                 "8240"
  36 #endif
  37 #ifdef CONFIG_MPC8245
  38                 "8245"
  39 #endif
  40                 " ##Test not implemented yet##\n");
  41         return 0;
  42 }
  43
  44 #if 0   /* NOT USED */
  45 int checkflash (void)
  46 {
  47         /* TODO: XXX XXX XXX */
  48         printf ("## Test not implemented yet ##\n");
  49
  50         return (0);
  51 }
  52 #endif
  53
  54 long int initdram (int board_type)
  55 {
  56         int m, row, col, bank, i;
  57         unsigned long start, end;
  58         uint32_t mccr1;
  59         uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
  60         uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
  61         uint8_t mber = 0;
  62
  63         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
  64
  65         if (i2c_reg_read (0x50, 2) != 0x04) return 0;   /* Memory type */
  66         m = i2c_reg_read (0x50, 5);     /* # of physical banks */
  67         row = i2c_reg_read (0x50, 3);   /* # of rows */
  68         col = i2c_reg_read (0x50, 4);   /* # of columns */
  69         bank = i2c_reg_read (0x50, 17); /* # of logical banks */
  70
  71         CONFIG_READ_WORD(MCCR1, mccr1);
  72         mccr1 &= 0xffff0000;
  73
  74         start = CFG_SDRAM_BASE;
  75         end = start + (1 << (col + row + 3) ) * bank - 1;
  76
  77         for (i = 0; i < m; i++) {
  78                 mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
  79                 if (i < 4) {
  80                         msar1  |= ((start >> 20) & 0xff) << i * 8;
  81                         emsar1 |= ((start >> 28) & 0xff) << i * 8;
  82                         mear1  |= ((end >> 20) & 0xff) << i * 8;
  83                         emear1 |= ((end >> 28) & 0xff) << i * 8;
  84                 } else {
  85                         msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
  86                         emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
  87                         mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
  88                         emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
  89                 }
  90                 mber |= 1 << i;
  91                 start += (1 << (col + row + 3) ) * bank;
  92                 end += (1 << (col + row + 3) ) * bank;
  93         }
  94         for (; i < 8; i++) {
  95                 if (i < 4) {
  96                         msar1  |= 0xff << i * 8;
  97                         emsar1 |= 0x30 << i * 8;
  98                         mear1  |= 0xff << i * 8;
  99                         emear1 |= 0x30 << i * 8;
 100                 } else {
 101                         msar2  |= 0xff << (i-4) * 8;
 102                         emsar2 |= 0x30 << (i-4) * 8;
 103                         mear2  |= 0xff << (i-4) * 8;
 104                         emear2 |= 0x30 << (i-4) * 8;
 105                 }
 106         }
 107
 108         CONFIG_WRITE_WORD(MCCR1, mccr1);
 109         CONFIG_WRITE_WORD(MSAR1, msar1);
 110         CONFIG_WRITE_WORD(EMSAR1, emsar1);
 111         CONFIG_WRITE_WORD(MEAR1, mear1);
 112         CONFIG_WRITE_WORD(EMEAR1, emear1);
 113         CONFIG_WRITE_WORD(MSAR2, msar2);
 114         CONFIG_WRITE_WORD(EMSAR2, emsar2);
 115         CONFIG_WRITE_WORD(MEAR2, mear2);
 116         CONFIG_WRITE_WORD(EMEAR2, emear2);
 117         CONFIG_WRITE_BYTE(MBER, mber);
 118
 119         return (1 << (col + row + 3) ) * bank * m;
 120 }
 121
 122 /*
 123  * Initialize PCI Devices, report devices found.
 124  */
 125 #ifndef CONFIG_PCI_PNP
 126 static struct pci_config_table pci_debris_config_table[] = {
 127         { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
 128           pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
 129                                        PCI_ENET0_MEMADDR,
 130                                        PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
 131         { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
 132           pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
 133                                        PCI_ENET1_MEMADDR,
 134                                        PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
 135         { }
 136 };
 137 #endif
 138
 139 struct pci_controller hose = {
 140 #ifndef CONFIG_PCI_PNP
 141         config_table: pci_debris_config_table,
 142 #endif
 143 };
 144
 145 void pci_init_board(void)
 146 {
 147         pci_mpc824x_init(&hose);
 148 }
 149
 150 void *nvram_read(void *dest, const long src, size_t count)
 151 {
 152         volatile uchar *d = (volatile uchar*) dest;
 153         volatile uchar *s = (volatile uchar*) src;
 154         while(count--) {
 155                 *d++ = *s++;
 156                 asm volatile("sync");
 157         }
 158         return dest;
 159 }
 160
 161 void nvram_write(long dest, const void *src, size_t count)
 162 {
 163         volatile uchar *d = (volatile uchar*)dest;
 164         volatile uchar *s = (volatile uchar*)src;
 165         while(count--) {
 166                 *d++ = *s++;
 167                 asm volatile("sync");
 168         }
 169 }
 170
 171 int misc_init_r(void)
 172 {
 173         DECLARE_GLOBAL_DATA_PTR;
 174
 175         /* Write ethernet addr in NVRAM for VxWorks */
 176         nvram_write(CFG_ENV_ADDR + CFG_NVRAM_VXWORKS_OFFS,
 177                         (char*)&gd->bd->bi_enetaddr[0], 6);
 178         return 0;
 179 }