board/evb64260/evb64260.c

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * evb64260.c - main board support/init for the Galileo Eval board.
  26  */
  27
  28 #include <common.h>
  29 #include <74xx_7xx.h>
  30 #include <galileo/memory.h>
  31 #include <galileo/pci.h>
  32 #include <galileo/gt64260R.h>
  33 #include <net.h>
  34
  35 #include <asm/io.h>
  36 #include "eth.h"
  37 #include "mpsc.h"
  38 #include "i2c.h"
  39 #include "64260.h"
  40 #ifdef CONFIG_ZUMA_V2
  41 extern void zuma_mbox_init(void);
  42 #endif
  43
  44 #undef  DEBUG
  45 #define MAP_PCI
  46
  47 #ifdef DEBUG
  48 #define DP(x) x
  49 #else
  50 #define DP(x)
  51 #endif
  52
  53 /* ------------------------------------------------------------------------- */
  54
  55 /* this is the current GT register space location */
  56 /* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
  57
  58 /* Unfortunately, we cant change it while we are in flash, so we initialize it
  59  * to the "final" value. This means that any debug_led calls before
  60  * board_early_init_f wont work right (like in cpu_init_f).
  61  * See also my_remap_gt_regs below. (NTL)
  62  */
  63
  64 unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
  65
  66 /* ------------------------------------------------------------------------- */
  67
  68 /*
  69  * This is a version of the GT register space remapping function that
  70  * doesn't touch globals (meaning, it's ok to run from flash.)
  71  *
  72  * Unfortunately, this has the side effect that a writable
  73  * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
  74  */
  75
  76 void
  77 my_remap_gt_regs(u32 cur_loc, u32 new_loc)
  78 {
  79         u32 temp;
  80
  81         /* check and see if it's already moved */
  82         temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
  83         if ((temp & 0xffff) == new_loc >> 20)
  84                 return;
  85
  86         temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
  87                 0xffff0000) | (new_loc >> 20);
  88
  89         out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
  90
  91         while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
  92 }
  93
  94 static void
  95 gt_pci_config(void)
  96 {
  97         /* move PCI stuff out of the way - NTL */
  98         /* map PCI Host 0 */
  99         pciMapSpace(PCI_HOST0, PCI_REGION0, CFG_PCI0_0_MEM_SPACE,
 100                 CFG_PCI0_0_MEM_SPACE, CFG_PCI0_MEM_SIZE);
 101
 102         pciMapSpace(PCI_HOST0, PCI_REGION1, 0, 0, 0);
 103         pciMapSpace(PCI_HOST0, PCI_REGION2, 0, 0, 0);
 104         pciMapSpace(PCI_HOST0, PCI_REGION3, 0, 0, 0);
 105
 106         pciMapSpace(PCI_HOST0, PCI_IO, CFG_PCI0_IO_SPACE_PCI,
 107                 CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE);
 108
 109         /* map PCI Host 1 */
 110         pciMapSpace(PCI_HOST1, PCI_REGION0, CFG_PCI1_0_MEM_SPACE,
 111                 CFG_PCI1_0_MEM_SPACE, CFG_PCI1_MEM_SIZE);
 112
 113         pciMapSpace(PCI_HOST1, PCI_REGION1, 0, 0, 0);
 114         pciMapSpace(PCI_HOST1, PCI_REGION2, 0, 0, 0);
 115         pciMapSpace(PCI_HOST1, PCI_REGION3, 0, 0, 0);
 116
 117         pciMapSpace(PCI_HOST1, PCI_IO, CFG_PCI1_IO_SPACE_PCI,
 118                 CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE);
 119
 120         /* PCI interface settings */
 121         GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff);
 122         GT_REG_WRITE(PCI_1TIMEOUT_RETRY, 0xffff);
 123         GT_REG_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
 124         GT_REG_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
 125
 126
 127 }
 128
 129 /* Setup CPU interface paramaters */
 130 static void
 131 gt_cpu_config(void)
 132 {
 133         cpu_t cpu = get_cpu_type();
 134         ulong tmp;
 135
 136         /* cpu configuration register */
 137         tmp = GTREGREAD(CPU_CONFIGURATION);
 138
 139         /* set the AACK delay bit
 140          * see Res#14 */
 141         tmp |= CPU_CONF_AACK_DELAY;
 142         tmp &= ~CPU_CONF_AACK_DELAY_2; /* New RGF */
 143
 144         /* Galileo claims this is necessary for all busses >= 100 MHz */
 145         tmp |= CPU_CONF_FAST_CLK;
 146
 147         if (cpu == CPU_750CX) {
 148                 tmp &= ~CPU_CONF_DP_VALID; /* Safer, needed for CXe. RGF */
 149                 tmp &= ~CPU_CONF_AP_VALID;
 150         } else {
 151                 tmp |= CPU_CONF_DP_VALID;
 152                 tmp |= CPU_CONF_AP_VALID;
 153         }
 154
 155         /* this only works with the MPX bus */
 156         tmp &= ~CPU_CONF_RD_OOO; /* Safer RGF */
 157         tmp |= CPU_CONF_PIPELINE;
 158         tmp |= CPU_CONF_TA_DELAY;
 159
 160         GT_REG_WRITE(CPU_CONFIGURATION, tmp);
 161
 162         /* CPU master control register */
 163         tmp = GTREGREAD(CPU_MASTER_CONTROL);
 164
 165         tmp |= CPU_MAST_CTL_ARB_EN;
 166
 167         if ((cpu == CPU_7400) ||
 168             (cpu == CPU_7410) ||
 169             (cpu == CPU_7450)) {
 170
 171                 tmp |= CPU_MAST_CTL_CLEAN_BLK;
 172                 tmp |= CPU_MAST_CTL_FLUSH_BLK;
 173
 174         } else {
 175                 /* cleanblock must be cleared for CPUs
 176                  * that do not support this command
 177                  * see Res#1 */
 178                 tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
 179                 tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
 180         }
 181         GT_REG_WRITE(CPU_MASTER_CONTROL, tmp);
 182 }
 183
 184 /*
 185  * board_early_init_f.
 186  *
 187  * set up gal. device mappings, etc.
 188  */
 189 int board_early_init_f (void)
 190 {
 191         uchar sram_boot = 0;
 192
 193         /*
 194          * set up the GT the way the kernel wants it
 195          * the call to move the GT register space will obviously
 196          * fail if it has already been done, but we're going to assume
 197          * that if it's not at the power-on location, it's where we put
 198          * it last time. (huber)
 199          */
 200         my_remap_gt_regs(CFG_DFL_GT_REGS, CFG_GT_REGS);
 201
 202         gt_pci_config();
 203
 204         /* mask all external interrupt sources */
 205         GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
 206         GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
 207         GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
 208         GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
 209         GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
 210         GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
 211         GT_REG_WRITE(CPU_INT_0_MASK, 0);
 212         GT_REG_WRITE(CPU_INT_1_MASK, 0);
 213         GT_REG_WRITE(CPU_INT_2_MASK, 0);
 214         GT_REG_WRITE(CPU_INT_3_MASK, 0);
 215
 216         /* now, onto the configuration */
 217         GT_REG_WRITE(SDRAM_CONFIGURATION, CFG_SDRAM_CONFIG);
 218
 219         /* ----- DEVICE BUS SETTINGS ------ */
 220
 221         /*
 222          * EVB
 223          * 0 - SRAM
 224          * 1 - RTC
 225          * 2 - UART
 226          * 3 - Flash
 227          * boot - BootCS
 228          *
 229          * Zuma
 230          * 0 - Flash
 231          * boot - BootCS
 232          */
 233
 234         /*
 235          * the dual 7450 module requires burst access to the boot
 236          * device, so the serial rom copies the boot device to the
 237          * on-board sram on the eval board, and updates the correct
 238          * registers to boot from the sram. (device0)
 239          */
 240 #if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
 241         /* Zuma has no SRAM */
 242         sram_boot = 0;
 243 #else
 244         if (memoryGetDeviceBaseAddress(DEVICE0) && 0xfff00000 == CFG_MONITOR_BASE)
 245                 sram_boot = 1;
 246 #endif
 247
 248         if (!sram_boot)
 249                 memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
 250
 251         memoryMapDeviceSpace(DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
 252         memoryMapDeviceSpace(DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
 253         memoryMapDeviceSpace(DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
 254
 255         /* configure device timing */
 256 #ifdef CFG_DEV0_PAR
 257         if (!sram_boot)
 258                 GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
 259 #endif
 260
 261 #ifdef CFG_DEV1_PAR
 262         GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
 263 #endif
 264 #ifdef CFG_DEV2_PAR
 265         GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
 266 #endif
 267
 268 #ifdef CONFIG_EVB64260
 269 #ifdef CFG_32BIT_BOOT_PAR
 270         /* detect if we are booting from the 32 bit flash */
 271         if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
 272                 /* 32 bit boot flash */
 273                 GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
 274                 GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_32BIT_BOOT_PAR);
 275         } else {
 276                 /* 8 bit boot flash */
 277                 GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
 278                 GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
 279         }
 280 #else
 281         /* 8 bit boot flash only */
 282         GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
 283 #endif
 284 #else /* CONFIG_EVB64260 not defined */
 285                 /* We are booting from 16-bit flash.
 286                  */
 287         GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_16BIT_BOOT_PAR);
 288 #endif
 289
 290         gt_cpu_config();
 291
 292         /* MPP setup */
 293         GT_REG_WRITE(MPP_CONTROL0, CFG_MPP_CONTROL_0);
 294         GT_REG_WRITE(MPP_CONTROL1, CFG_MPP_CONTROL_1);
 295         GT_REG_WRITE(MPP_CONTROL2, CFG_MPP_CONTROL_2);
 296         GT_REG_WRITE(MPP_CONTROL3, CFG_MPP_CONTROL_3);
 297
 298         GT_REG_WRITE(GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
 299         GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CFG_SERIAL_PORT_MUX);
 300
 301         return 0;
 302 }
 303
 304 /* various things to do after relocation */
 305
 306 int misc_init_r (void)
 307 {
 308         icache_enable();
 309 #ifdef CFG_L2
 310         l2cache_enable();
 311 #endif
 312
 313 #ifdef CONFIG_MPSC
 314         mpsc_init2();
 315 #endif
 316
 317 #ifdef CONFIG_ZUMA_V2
 318         zuma_mbox_init();
 319 #endif
 320         return (0);
 321 }
 322
 323 void
 324 after_reloc(ulong dest_addr)
 325 {
 326         DECLARE_GLOBAL_DATA_PTR;
 327
 328         /* check to see if we booted from the sram.  If so, move things
 329          * back to the way they should be. (we're running from main
 330          * memory at this point now */
 331
 332         if (memoryGetDeviceBaseAddress(DEVICE0) == CFG_MONITOR_BASE) {
 333                 memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
 334                 memoryMapDeviceSpace(BOOT_DEVICE, CFG_FLASH_BASE, _1M);
 335         }
 336
 337         /* now, jump to the main U-Boot board init code */
 338         board_init_r ((gd_t *)gd, dest_addr);
 339
 340         /* NOTREACHED */
 341 }
 342
 343 /* ------------------------------------------------------------------------- */
 344
 345 /*
 346  * Check Board Identity:
 347  */
 348
 349 int
 350 checkboard (void)
 351 {
 352         puts ("Board: " CFG_BOARD_NAME "\n");
 353         return (0);
 354 }
 355
 356 /* utility functions */
 357 void
 358 debug_led(int led, int mode)
 359 {
 360 #if !defined(CONFIG_ZUMA_V2) && !defined(CONFIG_P3G4)
 361         volatile int *addr = NULL;
 362         int dummy;
 363
 364         if (mode == 1) {
 365                 switch (led) {
 366                 case 0:
 367                         addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x08000);
 368                         break;
 369
 370                 case 1:
 371                         addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x0c000);
 372                         break;
 373
 374                 case 2:
 375                         addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x10000);
 376                         break;
 377                 }
 378         } else if (mode == 0) {
 379                 switch (led) {
 380                 case 0:
 381                         addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x14000);
 382                         break;
 383
 384                 case 1:
 385                         addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x18000);
 386                         break;
 387
 388                 case 2:
 389                         addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x1c000);
 390                         break;
 391                 }
 392         }
 393         WRITE_CHAR(addr, 0);
 394         dummy = *addr;
 395 #endif /* CONFIG_ZUMA_V2 */
 396 }
 397
 398 void
 399 display_mem_map(void)
 400 {
 401     int i,j;
 402     unsigned int base,size,width;
 403     /* SDRAM */
 404     printf("SDRAM\n");
 405     for(i=0;i<=BANK3;i++) {
 406         base = memoryGetBankBaseAddress(i);
 407         size = memoryGetBankSize(i);
 408         if(size !=0)
 409         {
 410             printf("BANK%d: base - 0x%08x\tsize - %dM bytes\n",i,base,size>>20);
 411         }
 412     }
 413
 414     /* CPU's PCI windows */
 415     for(i=0;i<=PCI_HOST1;i++) {
 416         printf("\nCPU's PCI %d windows\n", i);
 417         base=pciGetSpaceBase(i,PCI_IO);
 418         size=pciGetSpaceSize(i,PCI_IO);
 419         printf("      IO: base - 0x%08x\tsize - %dM bytes\n",base,size>>20);
 420         for(j=0;j<=PCI_REGION3;j++) {
 421             base = pciGetSpaceBase(i,j);
 422             size = pciGetSpaceSize(i,j);
 423             printf("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",j,base,
 424                     size>>20);
 425         }
 426     }
 427
 428     /* Devices */
 429     printf("\nDEVICES\n");
 430         for(i=0;i<=DEVICE3;i++) {
 431         base = memoryGetDeviceBaseAddress(i);
 432         size = memoryGetDeviceSize(i);
 433         width= memoryGetDeviceWidth(i) * 8;
 434         printf("DEV %d:  base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
 435                i, base, size>>20, width);
 436     }
 437
 438     /* Bootrom */
 439     base = memoryGetDeviceBaseAddress(BOOT_DEVICE); /* Boot */
 440     size = memoryGetDeviceSize(BOOT_DEVICE);
 441     width= memoryGetDeviceWidth(BOOT_DEVICE) * 8;
 442     printf(" BOOT:  base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
 443            base, size>>20, width);
 444 }