3 * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * mpsc.c - driver for console over the MPSC.
30 #include <asm/cache.h>
35 int (*mpsc_putchar
)(char ch
) = mpsc_putchar_early
;
37 static volatile unsigned int *rx_desc_base
=NULL
;
38 static unsigned int rx_desc_index
=0;
39 static volatile unsigned int *tx_desc_base
=NULL
;
40 static unsigned int tx_desc_index
=0;
42 /* local function declarations */
43 static int galmpsc_connect(int channel
, int connect
);
44 static int galmpsc_route_serial(int channel
, int connect
);
45 static int galmpsc_route_rx_clock(int channel
, int brg
);
46 static int galmpsc_route_tx_clock(int channel
, int brg
);
47 static int galmpsc_write_config_regs(int mpsc
, int mode
);
48 static int galmpsc_config_channel_regs(int mpsc
);
49 static int galmpsc_set_char_length(int mpsc
, int value
);
50 static int galmpsc_set_stop_bit_length(int mpsc
, int value
);
51 static int galmpsc_set_parity(int mpsc
, int value
);
52 static int galmpsc_enter_hunt(int mpsc
);
53 static int galmpsc_set_brkcnt(int mpsc
, int value
);
54 static int galmpsc_set_tcschar(int mpsc
, int value
);
55 static int galmpsc_set_snoop(int mpsc
, int value
);
56 static int galmpsc_shutdown(int mpsc
);
58 static int galsdma_set_RFT(int channel
);
59 static int galsdma_set_SFM(int channel
);
60 static int galsdma_set_rxle(int channel
);
61 static int galsdma_set_txle(int channel
);
62 static int galsdma_set_burstsize(int channel
, unsigned int value
);
63 static int galsdma_set_RC(int channel
, unsigned int value
);
65 static int galbrg_set_CDV(int channel
, int value
);
66 static int galbrg_enable(int channel
);
67 static int galbrg_disable(int channel
);
68 static int galbrg_set_clksrc(int channel
, int value
);
69 static int galbrg_set_CUV(int channel
, int value
);
71 static void galsdma_enable_rx(void);
73 /* static int galbrg_reset(int channel); */
75 #define SOFTWARE_CACHE_MANAGEMENT
77 #ifdef SOFTWARE_CACHE_MANAGEMENT
78 #define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
79 #define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
80 #define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
82 #define FLUSH_DCACHE(a,b)
83 #define FLUSH_AND_INVALIDATE_DCACHE(a,b)
84 #define INVALIDATE_DCACHE(a,b)
88 /* GT64240A errata: cant read MPSC/BRG registers... so make mirrors in ram for read/modify write */
89 #define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->mirror_hack))
91 #define GT_REG_WRITE_MIRROR_G(a,d) {MIRROR_HACK->a ## _M = d; GT_REG_WRITE(a,d);}
92 #define GTREGREAD_MIRROR_G(a) (MIRROR_HACK->a ## _M)
94 #define GT_REG_WRITE_MIRROR(a,i,g,d) {MIRROR_HACK->a ## _M[i] = d; GT_REG_WRITE(a + (i*g),d);}
95 #define GTREGREAD_MIRROR(a,i,g) (MIRROR_HACK->a ## _M[i])
97 /* make sure this isn't bigger than 16 long words (u-boot.h) */
98 struct _tag_mirror_hack
{
99 unsigned GALMPSC_PROTOCONF_REG_M
[2]; /* 8008 */
100 unsigned GALMPSC_CHANNELREG_1_M
[2]; /* 800c */
101 unsigned GALMPSC_CHANNELREG_2_M
[2]; /* 8010 */
102 unsigned GALBRG_0_CONFREG_M
[2]; /* b200 */
104 unsigned GALMPSC_ROUTING_REGISTER_M
; /* b400 */
105 unsigned GALMPSC_RxC_ROUTE_M
; /* b404 */
106 unsigned GALMPSC_TxC_ROUTE_M
; /* b408 */
108 unsigned int baudrate
; /* current baudrate, for tsc delay calc */
111 /* static struct _tag_mirror_hack *mh = NULL; */
113 /* special function for running out of flash. doesn't modify any
114 * global variables [josh] */
116 mpsc_putchar_early(char ch
)
118 DECLARE_GLOBAL_DATA_PTR
;
120 int temp
=GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2
,mpsc
,GALMPSC_REG_GAP
);
121 galmpsc_set_tcschar(mpsc
,ch
);
122 GT_REG_WRITE(GALMPSC_CHANNELREG_2
+(mpsc
*GALMPSC_REG_GAP
), temp
|0x200);
124 #define MAGIC_FACTOR (10*1000000)
126 udelay(MAGIC_FACTOR
/ MIRROR_HACK
->baudrate
);
130 /* This is used after relocation, see serial.c and mpsc_init2 */
132 mpsc_putchar_sdma(char ch
)
134 volatile unsigned int *p
;
138 /* align the descriptor */
140 memset((void *)p
, 0, 8 * sizeof(unsigned int));
142 /* fill one 64 bit buffer */
143 /* word swap, pad with 0 */
145 p
[5] = (unsigned int)ch
; /* x */
147 /* CHANGED completely according to GT64260A dox - NTL */
148 p
[0] = 0x00010001; /* 0 */
149 p
[1] = DESC_OWNER
| DESC_FIRST
| DESC_LAST
; /* 4 */
151 p
[3] = (unsigned int)&p
[4]; /* c */
154 p
[9] = DESC_FIRST
| DESC_LAST
;
155 p
[10] = (unsigned int)&p
[0];
156 p
[11] = (unsigned int)&p
[12];
159 FLUSH_DCACHE(&p
[0], &p
[8]);
161 GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR
+(CHANNEL
*GALSDMA_REG_DIFF
),
162 (unsigned int)&p
[0]);
163 GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR
+(CHANNEL
*GALSDMA_REG_DIFF
),
164 (unsigned int)&p
[0]);
166 temp
= GTREGREAD(GALSDMA_0_COM_REG
+(CHANNEL
*GALSDMA_REG_DIFF
));
167 temp
|= (TX_DEMAND
| TX_STOP
);
168 GT_REG_WRITE(GALSDMA_0_COM_REG
+(CHANNEL
*GALSDMA_REG_DIFF
), temp
);
170 INVALIDATE_DCACHE(&p
[1], &p
[2]);
172 while(p
[1] & DESC_OWNER
) {
174 INVALIDATE_DCACHE(&p
[1], &p
[2]);
183 DECLARE_GLOBAL_DATA_PTR
;
184 static unsigned int done
= 0;
186 unsigned int len
=0, idx
=0, temp
;
188 volatile unsigned int *p
;
192 p
=&rx_desc_base
[rx_desc_index
*8];
194 INVALIDATE_DCACHE(&p
[0], &p
[1]);
195 /* Wait for character */
196 while (p
[1] & DESC_OWNER
){
198 INVALIDATE_DCACHE(&p
[0], &p
[1]);
201 /* Handle error case */
202 if (p
[1] & (1<<15)) {
203 printf("oops, error: %08x\n", p
[1]);
205 temp
= GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2
,CHANNEL
,GALMPSC_REG_GAP
);
207 GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2
, CHANNEL
,GALMPSC_REG_GAP
, temp
);
209 /* Can't poll on abort bit, so we just wait. */
215 /* Number of bytes left in this descriptor */
221 if (done
> 3) idx
= 4;
222 if (done
> 7) idx
= 7;
223 if (done
> 11) idx
= 6;
225 INVALIDATE_DCACHE(&p
[idx
], &p
[idx
+1]);
231 /* this descriptor has more bytes still
232 * shift down the char we just read, and leave the
233 * buffer in place for the next time around
235 p
[idx
] = p
[idx
] >> 8;
236 FLUSH_DCACHE(&p
[idx
], &p
[idx
+1]);
240 /* nothing left in this descriptor.
243 p
[1] = DESC_OWNER
| DESC_FIRST
| DESC_LAST
;
245 FLUSH_DCACHE(&p
[0], &p
[1]);
246 /* Next descriptor */
247 rx_desc_index
= (rx_desc_index
+ 1) % RX_DESC
;
250 } while (len
==0); /* galileo bug.. len might be zero */
258 volatile unsigned int *p
=&rx_desc_base
[rx_desc_index
*8];
260 INVALIDATE_DCACHE(&p
[1], &p
[2]);
262 if (p
[1] & DESC_OWNER
) return 0;
269 DECLARE_GLOBAL_DATA_PTR
;
271 memset(MIRROR_HACK
, 0, sizeof(struct _tag_mirror_hack
));
272 MIRROR_HACK
->GALMPSC_ROUTING_REGISTER_M
=0x3fffffff;
275 galbrg_set_baudrate(CHANNEL
, baud
);
276 #if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
277 galbrg_set_clksrc(CHANNEL
,0x8); /* connect TCLK -> BRG */
279 galbrg_set_clksrc(CHANNEL
,0);
281 galbrg_set_CUV(CHANNEL
, 0);
282 galbrg_enable(CHANNEL
);
284 /* Set up clock routing */
285 galmpsc_connect(CHANNEL
, GALMPSC_CONNECT
);
286 galmpsc_route_serial(CHANNEL
, GALMPSC_CONNECT
);
287 galmpsc_route_rx_clock(CHANNEL
, CHANNEL
);
288 galmpsc_route_tx_clock(CHANNEL
, CHANNEL
);
290 /* reset MPSC state */
291 galmpsc_shutdown(CHANNEL
);
294 galsdma_set_burstsize(CHANNEL
, L1_CACHE_BYTES
/8); /* in 64 bit words (8 bytes) */
295 galsdma_set_txle(CHANNEL
);
296 galsdma_set_rxle(CHANNEL
);
297 galsdma_set_RC(CHANNEL
, 0xf);
298 galsdma_set_SFM(CHANNEL
);
299 galsdma_set_RFT(CHANNEL
);
302 galmpsc_write_config_regs(CHANNEL
, GALMPSC_UART
);
303 galmpsc_config_channel_regs(CHANNEL
);
304 galmpsc_set_char_length(CHANNEL
, GALMPSC_CHAR_LENGTH_8
); /* 8 */
305 galmpsc_set_parity(CHANNEL
, GALMPSC_PARITY_NONE
); /* N */
306 galmpsc_set_stop_bit_length(CHANNEL
, GALMPSC_STOP_BITS_1
); /* 1 */
308 /* COMM_MPSC CONFIG */
309 #ifdef SOFTWARE_CACHE_MANAGEMENT
310 galmpsc_set_snoop(CHANNEL
, 0); /* disable snoop */
312 galmpsc_set_snoop(CHANNEL
, 1); /* enable snoop */
323 mpsc_putchar
= mpsc_putchar_sdma
;
326 rx_desc_base
= (unsigned int *)malloc(((RX_DESC
+1)*8) *
327 sizeof(unsigned int));
329 /* align descriptors */
330 rx_desc_base
= (unsigned int *)
331 (((unsigned int)rx_desc_base
+32) & 0xFFFFFFF0);
335 memset((void *)rx_desc_base
, 0, (RX_DESC
*8)*sizeof(unsigned int));
337 for (i
= 0; i
< RX_DESC
; i
++) {
338 rx_desc_base
[i
*8 + 3] = (unsigned int)&rx_desc_base
[i
*8 + 4]; /* Buffer */
339 rx_desc_base
[i
*8 + 2] = (unsigned int)&rx_desc_base
[(i
+1)*8]; /* Next descriptor */
340 rx_desc_base
[i
*8 + 1] = DESC_OWNER
| DESC_FIRST
| DESC_LAST
; /* Command & control */
341 rx_desc_base
[i
*8] = 0x00100000;
343 rx_desc_base
[(i
-1)*8 + 2] = (unsigned int)&rx_desc_base
[0];
345 FLUSH_DCACHE(&rx_desc_base
[0], &rx_desc_base
[RX_DESC
*8]);
346 GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR
+(CHANNEL
*GALSDMA_REG_DIFF
),
347 (unsigned int)&rx_desc_base
[0]);
350 tx_desc_base
= (unsigned int *)malloc(((TX_DESC
+1)*8) *
351 sizeof(unsigned int));
353 /* align descriptors */
354 tx_desc_base
= (unsigned int *)
355 (((unsigned int)tx_desc_base
+32) & 0xFFFFFFF0);
359 memset((void *)tx_desc_base
, 0, (TX_DESC
*8)*sizeof(unsigned int));
361 for (i
= 0; i
< TX_DESC
; i
++) {
362 tx_desc_base
[i
*8 + 5] = (unsigned int)0x23232323;
363 tx_desc_base
[i
*8 + 4] = (unsigned int)0x23232323;
364 tx_desc_base
[i
*8 + 3] = (unsigned int)&tx_desc_base
[i
*8 + 4];
365 tx_desc_base
[i
*8 + 2] = (unsigned int)&tx_desc_base
[(i
+1)*8];
366 tx_desc_base
[i
*8 + 1] = DESC_OWNER
| DESC_FIRST
| DESC_LAST
;
368 /* set sbytecnt and shadow byte cnt to 1 */
369 tx_desc_base
[i
*8] = 0x00010001;
371 tx_desc_base
[(i
-1)*8 + 2] = (unsigned int)&tx_desc_base
[0];
373 FLUSH_DCACHE(&tx_desc_base
[0], &tx_desc_base
[TX_DESC
*8]);
383 galbrg_set_baudrate(int channel
, int rate
)
385 DECLARE_GLOBAL_DATA_PTR
;
388 galbrg_disable(channel
);
390 #if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
392 clock
= (CFG_BUS_HZ
/(16*rate
)) - 1;
394 clock
= (3686400/(16*rate
)) - 1;
397 galbrg_set_CDV(channel
, clock
);
399 galbrg_enable(channel
);
401 MIRROR_HACK
->baudrate
= rate
;
406 /* ------------------------------------------------------------------ */
408 /* Below are all the private functions that no one else needs */
411 galbrg_set_CDV(int channel
, int value
)
413 DECLARE_GLOBAL_DATA_PTR
;
416 temp
= GTREGREAD_MIRROR(GALBRG_0_CONFREG
, channel
, GALBRG_REG_GAP
);
418 temp
|= (value
& 0x0000FFFF);
419 GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG
,channel
,GALBRG_REG_GAP
, temp
);
425 galbrg_enable(int channel
)
427 DECLARE_GLOBAL_DATA_PTR
;
430 temp
= GTREGREAD_MIRROR(GALBRG_0_CONFREG
, channel
, GALBRG_REG_GAP
);
432 GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG
, channel
, GALBRG_REG_GAP
,temp
);
438 galbrg_disable(int channel
)
440 DECLARE_GLOBAL_DATA_PTR
;
443 temp
= GTREGREAD_MIRROR(GALBRG_0_CONFREG
, channel
, GALBRG_REG_GAP
);
445 GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG
, channel
, GALBRG_REG_GAP
,temp
);
451 galbrg_set_clksrc(int channel
, int value
)
453 DECLARE_GLOBAL_DATA_PTR
;
456 temp
= GTREGREAD_MIRROR(GALBRG_0_CONFREG
,channel
, GALBRG_REG_GAP
);
458 temp
|= (value
<< 18);
459 GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG
,channel
, GALBRG_REG_GAP
,temp
);
465 galbrg_set_CUV(int channel
, int value
)
467 GT_REG_WRITE(GALBRG_0_BTREG
+ (channel
* GALBRG_REG_GAP
), value
);
474 galbrg_reset(int channel
)
478 temp
= GTREGREAD(GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
));
480 GT_REG_WRITE(GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
), temp
);
487 galsdma_set_RFT(int channel
)
491 temp
= GTREGREAD(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
));
493 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
), temp
);
499 galsdma_set_SFM(int channel
)
503 temp
= GTREGREAD(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
));
505 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
), temp
);
511 galsdma_set_rxle(int channel
)
515 temp
= GTREGREAD(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
));
517 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
), temp
);
523 galsdma_set_txle(int channel
)
527 temp
= GTREGREAD(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
));
529 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
), temp
);
535 galsdma_set_RC(int channel
, unsigned int value
)
539 temp
= GTREGREAD(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
));
541 temp
|= (value
<< 2);
542 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
), temp
);
548 galsdma_set_burstsize(int channel
, unsigned int value
)
552 temp
= GTREGREAD(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
));
556 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
),
557 (temp
| (0x3 << 12)));
561 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
),
562 (temp
| (0x2 << 12)));
566 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
),
567 (temp
| (0x1 << 12)));
571 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
),
572 (temp
| (0x0 << 12)));
584 galmpsc_connect(int channel
, int connect
)
586 DECLARE_GLOBAL_DATA_PTR
;
589 temp
= GTREGREAD_MIRROR_G(GALMPSC_ROUTING_REGISTER
);
591 if ((channel
== 0) && connect
)
593 else if ((channel
== 1) && connect
)
594 temp
&= ~(0x00000007 << 6);
595 else if ((channel
== 0) && !connect
)
598 temp
|= (0x00000007 << 6);
600 /* Just in case... */
603 GT_REG_WRITE_MIRROR_G(GALMPSC_ROUTING_REGISTER
, temp
);
609 galmpsc_route_serial(int channel
, int connect
)
613 temp
= GTREGREAD(GALMPSC_SERIAL_MULTIPLEX
);
615 if ((channel
== 0) && connect
)
617 else if ((channel
== 1) && connect
)
619 else if ((channel
== 0) && !connect
)
624 GT_REG_WRITE(GALMPSC_SERIAL_MULTIPLEX
,temp
);
630 galmpsc_route_rx_clock(int channel
, int brg
)
632 DECLARE_GLOBAL_DATA_PTR
;
635 temp
= GTREGREAD_MIRROR_G(GALMPSC_RxC_ROUTE
);
642 GT_REG_WRITE_MIRROR_G(GALMPSC_RxC_ROUTE
,temp
);
648 galmpsc_route_tx_clock(int channel
, int brg
)
650 DECLARE_GLOBAL_DATA_PTR
;
653 temp
= GTREGREAD_MIRROR_G(GALMPSC_TxC_ROUTE
);
660 GT_REG_WRITE_MIRROR_G(GALMPSC_TxC_ROUTE
,temp
);
666 galmpsc_write_config_regs(int mpsc
, int mode
)
668 if (mode
== GALMPSC_UART
) {
669 /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
670 GT_REG_WRITE(GALMPSC_MCONF_LOW
+ (mpsc
*GALMPSC_REG_GAP
),
673 /* Main config reg High (32x Rx/Tx clock mode, width=8bits */
674 GT_REG_WRITE(GALMPSC_MCONF_HIGH
+(mpsc
*GALMPSC_REG_GAP
),
678 /* 0000 0010 0000 0000 */
681 /* 0000 0011 1111 1000 */
689 galmpsc_config_channel_regs(int mpsc
)
691 DECLARE_GLOBAL_DATA_PTR
;
692 GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1
,mpsc
,GALMPSC_REG_GAP
, 0);
693 GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2
,mpsc
,GALMPSC_REG_GAP
, 0);
694 GT_REG_WRITE(GALMPSC_CHANNELREG_3
+(mpsc
*GALMPSC_REG_GAP
), 1);
695 GT_REG_WRITE(GALMPSC_CHANNELREG_4
+(mpsc
*GALMPSC_REG_GAP
), 0);
696 GT_REG_WRITE(GALMPSC_CHANNELREG_5
+(mpsc
*GALMPSC_REG_GAP
), 0);
697 GT_REG_WRITE(GALMPSC_CHANNELREG_6
+(mpsc
*GALMPSC_REG_GAP
), 0);
698 GT_REG_WRITE(GALMPSC_CHANNELREG_7
+(mpsc
*GALMPSC_REG_GAP
), 0);
699 GT_REG_WRITE(GALMPSC_CHANNELREG_8
+(mpsc
*GALMPSC_REG_GAP
), 0);
700 GT_REG_WRITE(GALMPSC_CHANNELREG_9
+(mpsc
*GALMPSC_REG_GAP
), 0);
701 GT_REG_WRITE(GALMPSC_CHANNELREG_10
+(mpsc
*GALMPSC_REG_GAP
), 0);
703 galmpsc_set_brkcnt(mpsc
, 0x3);
704 galmpsc_set_tcschar(mpsc
, 0xab);
710 galmpsc_set_brkcnt(int mpsc
, int value
)
712 DECLARE_GLOBAL_DATA_PTR
;
715 temp
= GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1
,mpsc
,GALMPSC_REG_GAP
);
717 temp
|= (value
<< 16);
718 GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1
,mpsc
,GALMPSC_REG_GAP
, temp
);
724 galmpsc_set_tcschar(int mpsc
, int value
)
726 DECLARE_GLOBAL_DATA_PTR
;
729 temp
= GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1
,mpsc
,GALMPSC_REG_GAP
);
732 GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1
,mpsc
,GALMPSC_REG_GAP
, temp
);
738 galmpsc_set_char_length(int mpsc
, int value
)
740 DECLARE_GLOBAL_DATA_PTR
;
743 temp
= GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG
,mpsc
,GALMPSC_REG_GAP
);
745 temp
|= (value
<< 12);
746 GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG
,mpsc
,GALMPSC_REG_GAP
, temp
);
752 galmpsc_set_stop_bit_length(int mpsc
, int value
)
754 DECLARE_GLOBAL_DATA_PTR
;
757 temp
= GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG
,mpsc
,GALMPSC_REG_GAP
);
758 temp
|= (value
<< 14);
759 GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG
,mpsc
,GALMPSC_REG_GAP
,temp
);
765 galmpsc_set_parity(int mpsc
, int value
)
767 DECLARE_GLOBAL_DATA_PTR
;
770 temp
= GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2
,mpsc
,GALMPSC_REG_GAP
);
773 temp
|= ((value
<< 18) | (value
<< 2));
774 temp
|= ((value
<< 17) | (value
<< 1));
779 GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2
,mpsc
,GALMPSC_REG_GAP
, temp
);
785 galmpsc_enter_hunt(int mpsc
)
787 DECLARE_GLOBAL_DATA_PTR
;
790 temp
= GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2
,mpsc
,GALMPSC_REG_GAP
);
792 GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2
,mpsc
,GALMPSC_REG_GAP
, temp
);
794 /* Should Poll on Enter Hunt bit, but the register is write-only */
795 /* errata suggests pausing 100 system cycles */
803 galmpsc_shutdown(int mpsc
)
805 DECLARE_GLOBAL_DATA_PTR
;
809 /* cause RX abort (clears RX) */
810 temp
= GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2
,mpsc
,GALMPSC_REG_GAP
);
811 temp
|= MPSC_RX_ABORT
| MPSC_TX_ABORT
;
812 temp
&= ~MPSC_ENTER_HUNT
;
813 GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2
,mpsc
,GALMPSC_REG_GAP
,temp
);
816 GT_REG_WRITE(GALSDMA_0_COM_REG
+ CHANNEL
* GALSDMA_REG_DIFF
, 0);
817 GT_REG_WRITE(GALSDMA_0_COM_REG
+ CHANNEL
* GALSDMA_REG_DIFF
,
818 SDMA_TX_ABORT
| SDMA_RX_ABORT
);
820 /* shut down the MPSC */
821 GT_REG_WRITE(GALMPSC_MCONF_LOW
, 0);
822 GT_REG_WRITE(GALMPSC_MCONF_HIGH
, 0);
823 GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG
, mpsc
, GALMPSC_REG_GAP
,0);
827 /* shut down the sdma engines. */
828 /* reset config to default */
829 GT_REG_WRITE(GALSDMA_0_CONF_REG
+ CHANNEL
* GALSDMA_REG_DIFF
,
834 /* clear the SDMA current and first TX and RX pointers */
835 GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR
+ CHANNEL
* GALSDMA_REG_DIFF
, 0);
836 GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR
+ CHANNEL
* GALSDMA_REG_DIFF
, 0);
837 GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR
+ CHANNEL
* GALSDMA_REG_DIFF
, 0);
845 galsdma_enable_rx(void)
849 /* Enable RX processing */
850 temp
= GTREGREAD(GALSDMA_0_COM_REG
+(CHANNEL
*GALSDMA_REG_DIFF
));
852 GT_REG_WRITE(GALSDMA_0_COM_REG
+(CHANNEL
*GALSDMA_REG_DIFF
), temp
);
854 galmpsc_enter_hunt(CHANNEL
);
858 galmpsc_set_snoop(int mpsc
, int value
)
860 int reg
= mpsc
? MPSC_1_ADDRESS_CONTROL_LOW
: MPSC_0_ADDRESS_CONTROL_LOW
;
861 int temp
=GTREGREAD(reg
);
863 temp
|= (1<< 6) | (1<<14) | (1<<22) | (1<<30);
865 temp
&= ~((1<< 6) | (1<<14) | (1<<22) | (1<<30));
866 GT_REG_WRITE(reg
, temp
);