2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 struct fsl_e_tlb_entry tlb_table
[] = {
11 /* TLB 0 - for temp stack in cache */
12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
,
13 CONFIG_SYS_INIT_RAM_ADDR_PHYS
,
14 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
15 0, 0, BOOKE_PAGESZ_4K
, 0),
16 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 4 * 1024,
17 CONFIG_SYS_INIT_RAM_ADDR_PHYS
+ 4 * 1024,
18 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
19 0, 0, BOOKE_PAGESZ_4K
, 0),
20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 8 * 1024,
21 CONFIG_SYS_INIT_RAM_ADDR_PHYS
+ 8 * 1024,
22 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
23 0, 0, BOOKE_PAGESZ_4K
, 0),
24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 12 * 1024,
25 CONFIG_SYS_INIT_RAM_ADDR_PHYS
+ 12 * 1024,
26 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
27 0, 0, BOOKE_PAGESZ_4K
, 0),
30 /* *I*** - Covers boot page */
31 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
33 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
34 * SRAM is at 0xfff00000, it covered the 0xfffff000.
36 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR
, CONFIG_SYS_INIT_L3_ADDR
,
37 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
38 0, 0, BOOKE_PAGESZ_1M
, 1),
39 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
41 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
42 * space is at 0xfff00000, it covered the 0xfffff000.
44 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR
,
45 CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS
,
46 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_W
|MAS2_G
,
47 0, 0, BOOKE_PAGESZ_1M
, 1),
49 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
50 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
51 0, 0, BOOKE_PAGESZ_4K
, 1),
55 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR
, CONFIG_SYS_CCSRBAR_PHYS
,
56 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
57 0, 1, BOOKE_PAGESZ_16M
, 1),
59 /* *I*G* - Flash, localbus */
60 /* This will be changed to *I*G* after relocation to RAM. */
61 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE
, CONFIG_SYS_FLASH_BASE_PHYS
,
62 MAS3_SX
|MAS3_SR
, MAS2_W
|MAS2_G
,
63 0, 2, BOOKE_PAGESZ_256M
, 1),
66 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT
, CONFIG_SYS_PCIE1_MEM_PHYS
,
67 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
68 0, 3, BOOKE_PAGESZ_256M
, 1),
70 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT
+ 0x10000000,
71 CONFIG_SYS_PCIE1_MEM_PHYS
+ 0x10000000,
72 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
73 0, 4, BOOKE_PAGESZ_256M
, 1),
76 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT
, CONFIG_SYS_PCIE1_IO_PHYS
,
77 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
78 0, 5, BOOKE_PAGESZ_64K
, 1),
81 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
82 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE
, CONFIG_SYS_BMAN_MEM_PHYS
,
83 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
84 0, 6, BOOKE_PAGESZ_16M
, 1),
85 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE
+ 0x01000000,
86 CONFIG_SYS_BMAN_MEM_PHYS
+ 0x01000000,
87 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
88 0, 7, BOOKE_PAGESZ_16M
, 1),
90 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
91 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE
, CONFIG_SYS_QMAN_MEM_PHYS
,
92 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
93 0, 8, BOOKE_PAGESZ_16M
, 1),
94 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE
+ 0x01000000,
95 CONFIG_SYS_QMAN_MEM_PHYS
+ 0x01000000,
96 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
97 0, 9, BOOKE_PAGESZ_16M
, 1),
99 #ifdef CONFIG_SYS_DCSRBAR_PHYS
100 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR
, CONFIG_SYS_DCSRBAR_PHYS
,
101 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
102 0, 10, BOOKE_PAGESZ_32M
, 1),
104 #ifdef CONFIG_SYS_NAND_BASE
108 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE
, CONFIG_SYS_NAND_BASE_PHYS
,
109 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
110 0, 11, BOOKE_PAGESZ_64K
, 1),
112 SET_TLB_ENTRY(1, QIXIS_BASE
, QIXIS_BASE_PHYS
,
113 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
114 0, 12, BOOKE_PAGESZ_4K
, 1),
118 * entry 14 and 15 has been used hard coded, they will be disabled
119 * in cpu_init_f, so we use entry 16 for SRIO2.
121 #ifdef CONFIG_SYS_SRIO1_MEM_PHYS
123 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT
, CONFIG_SYS_SRIO1_MEM_PHYS
,
124 MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
125 0, 13, BOOKE_PAGESZ_256M
, 1),
127 #ifdef CONFIG_SYS_SRIO2_MEM_PHYS
129 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT
, CONFIG_SYS_SRIO2_MEM_PHYS
,
130 MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
131 0, 16, BOOKE_PAGESZ_256M
, 1),
133 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
135 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
136 * fetching ucode and ENV from master
138 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR
,
139 CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS
,
140 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_G
,
141 0, 17, BOOKE_PAGESZ_1M
, 1),
145 int num_tlb_entries
= ARRAY_SIZE(tlb_table
);