2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
11 #include <fsl_ddr_sdram.h>
12 #include <fsl_ddr_dimm_params.h>
13 #include <asm/fsl_law.h>
15 DECLARE_GLOBAL_DATA_PTR
;
19 * Fixed sdram init -- doesn't use serial presence detect.
21 extern fixed_ddr_parm_t fixed_ddr_parm_0
[];
22 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
23 extern fixed_ddr_parm_t fixed_ddr_parm_1
[];
26 phys_size_t
fixed_sdram(void)
30 fsl_ddr_cfg_regs_t ddr_cfg_regs
;
32 unsigned int lawbar1_target_id
;
33 ulong ddr_freq
, ddr_freq_mhz
;
35 ddr_freq
= get_ddr_freq(0);
36 ddr_freq_mhz
= ddr_freq
/ 1000000;
38 printf("Configuring DDR for %s MT/s data rate\n",
39 strmhz(buf
, ddr_freq
));
41 for (i
= 0; fixed_ddr_parm_0
[i
].max_freq
> 0; i
++) {
42 if ((ddr_freq_mhz
> fixed_ddr_parm_0
[i
].min_freq
) &&
43 (ddr_freq_mhz
<= fixed_ddr_parm_0
[i
].max_freq
)) {
45 fixed_ddr_parm_0
[i
].ddr_settings
,
46 sizeof(ddr_cfg_regs
));
51 if (fixed_ddr_parm_0
[i
].max_freq
== 0)
52 panic("Unsupported DDR data rate %s MT/s data rate\n",
53 strmhz(buf
, ddr_freq
));
55 ddr_size
= (phys_size_t
) CONFIG_SYS_SDRAM_SIZE
* 1024 * 1024;
56 ddr_cfg_regs
.ddr_cdr1
= DDR_CDR1_DHC_EN
;
57 fsl_ddr_set_memctl_regs(&ddr_cfg_regs
, 0, 0);
59 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
61 fixed_ddr_parm_1
[i
].ddr_settings
,
62 sizeof(ddr_cfg_regs
));
63 ddr_cfg_regs
.ddr_cdr1
= DDR_CDR1_DHC_EN
;
64 fsl_ddr_set_memctl_regs(&ddr_cfg_regs
, 1, 0);
68 * setup laws for DDR. If not interleaving, presuming half memory on
69 * DDR1 and the other half on DDR2
71 if (fixed_ddr_parm_0
[i
].ddr_settings
->cs
[0].config
& 0x20000000) {
72 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE
,
74 LAW_TRGT_IF_DDR_INTRLV
) < 0) {
75 printf("ERROR setting Local Access Windows for DDR\n");
79 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
80 /* We require both controllers have identical DIMMs */
81 lawbar1_target_id
= LAW_TRGT_IF_DDR_1
;
82 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE
,
84 lawbar1_target_id
) < 0) {
85 printf("ERROR setting Local Access Windows for DDR\n");
88 lawbar1_target_id
= LAW_TRGT_IF_DDR_2
;
89 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE
+ ddr_size
/ 2,
91 lawbar1_target_id
) < 0) {
92 printf("ERROR setting Local Access Windows for DDR\n");
96 lawbar1_target_id
= LAW_TRGT_IF_DDR_1
;
97 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE
,
99 lawbar1_target_id
) < 0) {
100 printf("ERROR setting Local Access Windows for DDR\n");
108 struct board_specific_parameters
{
110 u32 datarate_mhz_high
;
114 u32 write_data_delay
;
119 * This table contains all valid speeds we want to override with board
120 * specific parameters. datarate_mhz_high values need to be in ascending order
121 * for each n_ranks group.
123 static const struct board_specific_parameters udimm0
[] = {
125 * memory controller 0
126 * num| hi| clk| wrlvl | cpo |wrdata|2T
127 * ranks| mhz|adjst| start | |delay |
129 {4, 850, 4, 6, 0xff, 2, 0},
130 {4, 950, 5, 7, 0xff, 2, 0},
131 {4, 1050, 5, 8, 0xff, 2, 0},
132 {4, 1250, 5, 10, 0xff, 2, 0},
133 {4, 1350, 5, 11, 0xff, 2, 0},
134 {4, 1666, 5, 12, 0xff, 2, 0},
135 {2, 850, 5, 6, 0xff, 2, 0},
136 {2, 1050, 5, 7, 0xff, 2, 0},
137 {2, 1250, 4, 6, 0xff, 2, 0},
138 {2, 1350, 5, 7, 0xff, 2, 0},
139 {2, 1666, 5, 8, 0xff, 2, 0},
140 {1, 1250, 4, 6, 0xff, 2, 0},
141 {1, 1335, 4, 7, 0xff, 2, 0},
142 {1, 1666, 4, 8, 0xff, 2, 0},
147 * The two slots have slightly different timing. The center values are good
148 * for both slots. We use identical speed tables for them. In future use, if
149 * DIMMs have fewer center values that require two separated tables, copy the
150 * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
152 static const struct board_specific_parameters
*udimms
[] = {
157 static const struct board_specific_parameters rdimm0
[] = {
159 * memory controller 0
160 * num| hi| clk| wrlvl | cpo |wrdata|2T
161 * ranks| mhz|adjst| start | |delay |
163 {4, 850, 4, 6, 0xff, 2, 0},
164 {4, 950, 5, 7, 0xff, 2, 0},
165 {4, 1050, 5, 8, 0xff, 2, 0},
166 {4, 1250, 5, 10, 0xff, 2, 0},
167 {4, 1350, 5, 11, 0xff, 2, 0},
168 {4, 1666, 5, 12, 0xff, 2, 0},
169 {2, 850, 4, 6, 0xff, 2, 0},
170 {2, 1050, 4, 7, 0xff, 2, 0},
171 {2, 1666, 4, 8, 0xff, 2, 0},
172 {1, 850, 4, 5, 0xff, 2, 0},
173 {1, 950, 4, 7, 0xff, 2, 0},
174 {1, 1666, 4, 8, 0xff, 2, 0},
179 * The two slots have slightly different timing. See comments above.
181 static const struct board_specific_parameters
*rdimms
[] = {
186 void fsl_ddr_board_options(memctl_options_t
*popts
,
187 dimm_params_t
*pdimm
,
188 unsigned int ctrl_num
)
190 const struct board_specific_parameters
*pbsp
, *pbsp_highest
= NULL
;
194 printf("Wrong parameter for controller number %d", ctrl_num
);
200 if (popts
->registered_dimm_en
)
201 pbsp
= rdimms
[ctrl_num
];
203 pbsp
= udimms
[ctrl_num
];
206 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
207 * freqency and n_banks specified in board_specific_parameters table.
209 ddr_freq
= get_ddr_freq(0) / 1000000;
210 while (pbsp
->datarate_mhz_high
) {
211 if (pbsp
->n_ranks
== pdimm
->n_ranks
) {
212 if (ddr_freq
<= pbsp
->datarate_mhz_high
) {
213 popts
->cpo_override
= pbsp
->cpo
;
214 popts
->write_data_delay
=
215 pbsp
->write_data_delay
;
216 popts
->clk_adjust
= pbsp
->clk_adjust
;
217 popts
->wrlvl_start
= pbsp
->wrlvl_start
;
218 popts
->twot_en
= pbsp
->force_2t
;
227 printf("Error: board specific timing not found "
228 "for data rate %lu MT/s!\n"
229 "Trying to use the highest speed (%u) parameters\n",
230 ddr_freq
, pbsp_highest
->datarate_mhz_high
);
231 popts
->cpo_override
= pbsp_highest
->cpo
;
232 popts
->write_data_delay
= pbsp_highest
->write_data_delay
;
233 popts
->clk_adjust
= pbsp_highest
->clk_adjust
;
234 popts
->wrlvl_start
= pbsp_highest
->wrlvl_start
;
235 popts
->twot_en
= pbsp_highest
->force_2t
;
237 panic("DIMM is not supported by this board");
241 * Factors to consider for half-strength driver enable:
242 * - number of DIMMs installed
244 popts
->half_strength_driver_enable
= 0;
246 * Write leveling override
248 popts
->wrlvl_override
= 1;
249 popts
->wrlvl_sample
= 0xf;
252 * Rtt and Rtt_WR override
254 popts
->rtt_override
= 0;
256 /* Enable ZQ calibration */
259 /* DHC_EN =1, ODT = 60 Ohm */
260 popts
->ddr_cdr1
= DDR_CDR1_DHC_EN
;
263 phys_size_t
initdram(int board_type
)
265 phys_size_t dram_size
;
267 puts("Initializing....");
271 dram_size
= fsl_ddr_sdram();
273 puts("using fixed parameters\n");
274 dram_size
= fixed_sdram();
277 dram_size
= setup_ddr_tlbs(dram_size
/ 0x100000);
278 dram_size
*= 0x100000;