board/freescale/ls1012ardb/ls1012ardb.c

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/fsl_serdes.h>
  12 #ifdef CONFIG_FSL_LS_PPA
  13 #include <asm/arch/ppa.h>
  14 #endif
  15 #include <asm/arch/mmu.h>
  16 #include <asm/arch/soc.h>
  17 #include <hwconfig.h>
  18 #include <ahci.h>
  19 #include <mmc.h>
  20 #include <scsi.h>
  21 #include <fsl_esdhc.h>
  22 #include <environment.h>
  23 #include <fsl_mmdc.h>
  24 #include <netdev.h>
  25 #include <fsl_sec.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 int checkboard(void)
  30 {
  31         u8 in1;
  32
  33         puts("Board: LS1012ARDB ");
  34
  35         /* Initialize i2c early for Serial flash bank information */
  36         i2c_set_bus_num(0);
  37
  38         if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
  39                 printf("Error reading i2c boot information!\n");
  40                 return 0; /* Don't want to hang() on this error */
  41         }
  42
  43         puts("Version");
  44         if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
  45                 puts(": RevA");
  46         else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
  47                 puts(": RevB");
  48         else
  49                 puts(": unknown");
  50
  51         printf(", boot from QSPI");
  52         if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
  53                 puts(": emu\n");
  54         else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
  55                 puts(": bank1\n");
  56         else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
  57                 puts(": bank2\n");
  58         else
  59                 puts("unknown\n");
  60
  61         return 0;
  62 }
  63
  64 int dram_init(void)
  65 {
  66         static const struct fsl_mmdc_info mparam = {
  67                 0x05180000,     /* mdctl */
  68                 0x00030035,     /* mdpdc */
  69                 0x12554000,     /* mdotc */
  70                 0xbabf7954,     /* mdcfg0 */
  71                 0xdb328f64,     /* mdcfg1 */
  72                 0x01ff00db,     /* mdcfg2 */
  73                 0x00001680,     /* mdmisc */
  74                 0x0f3c8000,     /* mdref */
  75                 0x00002000,     /* mdrwd */
  76                 0x00bf1023,     /* mdor */
  77                 0x0000003f,     /* mdasp */
  78                 0x0000022a,     /* mpodtctrl */
  79                 0xa1390003,     /* mpzqhwctrl */
  80         };
  81
  82         mmdc_init(&mparam);
  83
  84         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  85 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  86         /* This will break-before-make MMU for DDR */
  87         update_early_mmu_table();
  88 #endif
  89
  90         return 0;
  91 }
  92
  93 int board_eth_init(bd_t *bis)
  94 {
  95         return pci_eth_init(bis);
  96 }
  97
  98 int board_early_init_f(void)
  99 {
 100         fsl_lsch2_early_init_f();
 101
 102         return 0;
 103 }
 104
 105 int board_init(void)
 106 {
 107         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 108                                         CONFIG_SYS_CCI400_OFFSET);
 109         /*
 110          * Set CCI-400 control override register to enable barrier
 111          * transaction
 112          */
 113         out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 114
 115 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 116         erratum_a010315();
 117 #endif
 118
 119 #ifdef CONFIG_ENV_IS_NOWHERE
 120         gd->env_addr = (ulong)&default_environment[0];
 121 #endif
 122
 123 #ifdef CONFIG_FSL_CAAM
 124         sec_init();
 125 #endif
 126
 127 #ifdef CONFIG_FSL_LS_PPA
 128         ppa_init();
 129 #endif
 130         return 0;
 131 }
 132
 133 int esdhc_status_fixup(void *blob, const char *compat)
 134 {
 135         char esdhc0_path[] = "/soc/esdhc@1560000";
 136         char esdhc1_path[] = "/soc/esdhc@1580000";
 137         u8 io = 0;
 138         u8 mux_sdhc2;
 139
 140         do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 141                          sizeof("okay"), 1);
 142
 143         i2c_set_bus_num(0);
 144
 145         /*
 146          * The I2C IO-expander for mux select is used to control the muxing
 147          * of various onboard interfaces.
 148          *
 149          * IO1[3:2] indicates SDHC2 interface demultiplexer select lines.
 150          *      00 - SDIO wifi
 151          *      01 - GPIO (to Arduino)
 152          *      10 - eMMC Memory
 153          *      11 - SPI
 154          */
 155         if (i2c_read(I2C_MUX_IO1_ADDR, 0, 1, &io, 1) < 0) {
 156                 printf("Error reading i2c boot information!\n");
 157                 return 0; /* Don't want to hang() on this error */
 158         }
 159
 160         mux_sdhc2 = (io & 0x0c) >> 2;
 161         /* Enable SDHC2 only when use SDIO wifi and eMMC */
 162         if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
 163                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 164                                  sizeof("okay"), 1);
 165         else
 166                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 167                                  sizeof("disabled"), 1);
 168         return 0;
 169 }
 170
 171 int ft_board_setup(void *blob, bd_t *bd)
 172 {
 173         arch_fixup_fdt(blob);
 174
 175         ft_cpu_setup(blob, bd);
 176
 177         return 0;
 178 }