board/freescale/ls1012ardb/ls1012ardb.c

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/fsl_serdes.h>
  12 #ifdef CONFIG_FSL_LS_PPA
  13 #include <asm/arch/ppa.h>
  14 #endif
  15 #include <asm/arch/soc.h>
  16 #include <hwconfig.h>
  17 #include <ahci.h>
  18 #include <mmc.h>
  19 #include <scsi.h>
  20 #include <fsl_esdhc.h>
  21 #include <environment.h>
  22 #include <fsl_mmdc.h>
  23 #include <netdev.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 int checkboard(void)
  28 {
  29         u8 in1;
  30
  31         puts("Board: LS1012ARDB ");
  32
  33         /* Initialize i2c early for Serial flash bank information */
  34         i2c_set_bus_num(0);
  35
  36         if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
  37                 printf("Error reading i2c boot information!\n");
  38                 return 0; /* Don't want to hang() on this error */
  39         }
  40
  41         puts("Version");
  42         if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
  43                 puts(": RevA");
  44         else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
  45                 puts(": RevB");
  46         else
  47                 puts(": unknown");
  48
  49         printf(", boot from QSPI");
  50         if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
  51                 puts(": emu\n");
  52         else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
  53                 puts(": bank1\n");
  54         else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
  55                 puts(": bank2\n");
  56         else
  57                 puts("unknown\n");
  58
  59         return 0;
  60 }
  61
  62 int dram_init(void)
  63 {
  64         static const struct fsl_mmdc_info mparam = {
  65                 0x05180000,     /* mdctl */
  66                 0x00030035,     /* mdpdc */
  67                 0x12554000,     /* mdotc */
  68                 0xbabf7954,     /* mdcfg0 */
  69                 0xdb328f64,     /* mdcfg1 */
  70                 0x01ff00db,     /* mdcfg2 */
  71                 0x00001680,     /* mdmisc */
  72                 0x0f3c8000,     /* mdref */
  73                 0x00002000,     /* mdrwd */
  74                 0x00bf1023,     /* mdor */
  75                 0x0000003f,     /* mdasp */
  76                 0x0000022a,     /* mpodtctrl */
  77                 0xa1390003,     /* mpzqhwctrl */
  78         };
  79
  80         mmdc_init(&mparam);
  81
  82         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  83
  84         return 0;
  85 }
  86
  87 int board_eth_init(bd_t *bis)
  88 {
  89         return pci_eth_init(bis);
  90 }
  91
  92 int board_early_init_f(void)
  93 {
  94         fsl_lsch2_early_init_f();
  95
  96         return 0;
  97 }
  98
  99 int board_init(void)
 100 {
 101         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 102         /*
 103          * Set CCI-400 control override register to enable barrier
 104          * transaction
 105          */
 106         out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 107
 108 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 109         erratum_a010315();
 110 #endif
 111
 112 #ifdef CONFIG_ENV_IS_NOWHERE
 113         gd->env_addr = (ulong)&default_environment[0];
 114 #endif
 115
 116 #ifdef CONFIG_FSL_LS_PPA
 117         ppa_init();
 118 #endif
 119         return 0;
 120 }
 121
 122 int esdhc_status_fixup(void *blob, const char *compat)
 123 {
 124         char esdhc0_path[] = "/soc/esdhc@1560000";
 125         char esdhc1_path[] = "/soc/esdhc@1580000";
 126         u8 io = 0;
 127         u8 mux_sdhc2;
 128
 129         do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 130                          sizeof("okay"), 1);
 131
 132         i2c_set_bus_num(0);
 133
 134         /*
 135          * The I2C IO-expander for mux select is used to control the muxing
 136          * of various onboard interfaces.
 137          *
 138          * IO1[3:2] indicates SDHC2 interface demultiplexer select lines.
 139          *      00 - SDIO wifi
 140          *      01 - GPIO (to Arduino)
 141          *      10 - eMMC Memory
 142          *      11 - SPI
 143          */
 144         if (i2c_read(I2C_MUX_IO1_ADDR, 0, 1, &io, 1) < 0) {
 145                 printf("Error reading i2c boot information!\n");
 146                 return 0; /* Don't want to hang() on this error */
 147         }
 148
 149         mux_sdhc2 = (io & 0x0c) >> 2;
 150         /* Enable SDHC2 only when use SDIO wifi and eMMC */
 151         if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
 152                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 153                                  sizeof("okay"), 1);
 154         else
 155                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 156                                  sizeof("disabled"), 1);
 157         return 0;
 158 }
 159
 160 int ft_board_setup(void *blob, bd_t *bd)
 161 {
 162         arch_fixup_fdt(blob);
 163
 164         ft_cpu_setup(blob, bd);
 165
 166         return 0;
 167 }
 168
 169 void dram_init_banksize(void)
 170 {
 171         /*
 172          * gd->secure_ram tracks the location of secure memory.
 173          * It was set as if the memory starts from 0.
 174          * The address needs to add the offset of its bank.
 175          */
 176         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 177         if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
 178                 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
 179                 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
 180                 gd->bd->bi_dram[1].size = gd->ram_size -
 181                         CONFIG_SYS_DDR_BLOCK1_SIZE;
 182 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 183                 gd->arch.secure_ram = gd->bd->bi_dram[1].start +
 184                         gd->arch.secure_ram -
 185                         CONFIG_SYS_DDR_BLOCK1_SIZE;
 186                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 187 #endif
 188         } else {
 189                 gd->bd->bi_dram[0].size = gd->ram_size;
 190 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 191                 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
 192                         gd->arch.secure_ram;
 193                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 194 #endif
 195         }
 196 }