board/freescale/ls1021aqds/ls1021aqds.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/immap_ls102xa.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/fsl_serdes.h>
  13 #include <asm/arch/ls102xa_soc.h>
  14 #include <asm/arch/ls102xa_devdis.h>
  15 #include <asm/arch/ls102xa_sata.h>
  16 #include <hwconfig.h>
  17 #include <mmc.h>
  18 #include <fsl_csu.h>
  19 #include <fsl_esdhc.h>
  20 #include <fsl_ifc.h>
  21 #include <fsl_sec.h>
  22 #include <spl.h>
  23 #include <fsl_devdis.h>
  24 #include <fsl_validate.h>
  25 #include <fsl_ddr.h>
  26 #include "../common/sleep.h"
  27 #include "../common/qixis.h"
  28 #include "ls1021aqds_qixis.h"
  29 #ifdef CONFIG_U_QE
  30 #include <fsl_qe.h>
  31 #endif
  32
  33 #define PIN_MUX_SEL_CAN         0x03
  34 #define PIN_MUX_SEL_IIC2        0xa0
  35 #define PIN_MUX_SEL_RGMII       0x00
  36 #define PIN_MUX_SEL_SAI         0x0c
  37 #define PIN_MUX_SEL_SDHC        0x00
  38
  39 #define SET_SDHC_MUX_SEL(reg, value)    ((reg & 0x0f) | value)
  40 #define SET_EC_MUX_SEL(reg, value)      ((reg & 0xf0) | value)
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 enum {
  44         MUX_TYPE_CAN,
  45         MUX_TYPE_IIC2,
  46         MUX_TYPE_RGMII,
  47         MUX_TYPE_SAI,
  48         MUX_TYPE_SDHC,
  49         MUX_TYPE_SD_PCI4,
  50         MUX_TYPE_SD_PC_SA_SG_SG,
  51         MUX_TYPE_SD_PC_SA_PC_SG,
  52         MUX_TYPE_SD_PC_SG_SG,
  53 };
  54
  55 enum {
  56         GE0_CLK125,
  57         GE2_CLK125,
  58         GE1_CLK125,
  59 };
  60
  61 int checkboard(void)
  62 {
  63 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  64         char buf[64];
  65 #endif
  66 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
  67         u8 sw;
  68 #endif
  69
  70         puts("Board: LS1021AQDS\n");
  71
  72 #ifdef CONFIG_SD_BOOT
  73         puts("SD\n");
  74 #elif CONFIG_QSPI_BOOT
  75         puts("QSPI\n");
  76 #else
  77         sw = QIXIS_READ(brdcfg[0]);
  78         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  79
  80         if (sw < 0x8)
  81                 printf("vBank: %d\n", sw);
  82         else if (sw == 0x8)
  83                 puts("PromJet\n");
  84         else if (sw == 0x9)
  85                 puts("NAND\n");
  86         else if (sw == 0x15)
  87                 printf("IFCCard\n");
  88         else
  89                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  90 #endif
  91
  92 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  93         printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
  94                QIXIS_READ(id), QIXIS_READ(arch));
  95
  96         printf("FPGA:  v%d (%s), build %d\n",
  97                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  98                (int)qixis_read_minor());
  99 #endif
 100
 101         return 0;
 102 }
 103
 104 unsigned long get_board_sys_clk(void)
 105 {
 106         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 107
 108         switch (sysclk_conf & 0x0f) {
 109         case QIXIS_SYSCLK_64:
 110                 return 64000000;
 111         case QIXIS_SYSCLK_83:
 112                 return 83333333;
 113         case QIXIS_SYSCLK_100:
 114                 return 100000000;
 115         case QIXIS_SYSCLK_125:
 116                 return 125000000;
 117         case QIXIS_SYSCLK_133:
 118                 return 133333333;
 119         case QIXIS_SYSCLK_150:
 120                 return 150000000;
 121         case QIXIS_SYSCLK_160:
 122                 return 160000000;
 123         case QIXIS_SYSCLK_166:
 124                 return 166666666;
 125         }
 126         return 66666666;
 127 }
 128
 129 unsigned long get_board_ddr_clk(void)
 130 {
 131         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 132
 133         switch ((ddrclk_conf & 0x30) >> 4) {
 134         case QIXIS_DDRCLK_100:
 135                 return 100000000;
 136         case QIXIS_DDRCLK_125:
 137                 return 125000000;
 138         case QIXIS_DDRCLK_133:
 139                 return 133333333;
 140         }
 141         return 66666666;
 142 }
 143
 144 int select_i2c_ch_pca9547(u8 ch)
 145 {
 146         int ret;
 147
 148         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 149         if (ret) {
 150                 puts("PCA: failed to select proper channel\n");
 151                 return ret;
 152         }
 153
 154         return 0;
 155 }
 156
 157 int dram_init(void)
 158 {
 159         /*
 160          * When resuming from deep sleep, the I2C channel may not be
 161          * in the default channel. So, switch to the default channel
 162          * before accessing DDR SPD.
 163          */
 164         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 165         return initdram();
 166 }
 167
 168 #ifdef CONFIG_FSL_ESDHC
 169 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 170         {CONFIG_SYS_FSL_ESDHC_ADDR},
 171 };
 172
 173 int board_mmc_init(bd_t *bis)
 174 {
 175         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 176
 177         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 178 }
 179 #endif
 180
 181 int board_early_init_f(void)
 182 {
 183         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 184
 185 #ifdef CONFIG_TSEC_ENET
 186         /* clear BD & FR bits for BE BD's and frame data */
 187         clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 188 #endif
 189
 190 #ifdef CONFIG_FSL_IFC
 191         init_early_memctl_regs();
 192 #endif
 193
 194         arch_soc_init();
 195
 196 #if defined(CONFIG_DEEP_SLEEP)
 197         if (is_warm_boot())
 198                 fsl_dp_disable_console();
 199 #endif
 200
 201         return 0;
 202 }
 203
 204 #ifdef CONFIG_SPL_BUILD
 205 void board_init_f(ulong dummy)
 206 {
 207         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 208         unsigned int major;
 209
 210 #ifdef CONFIG_NAND_BOOT
 211         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 212         u32 porsr1, pinctl;
 213
 214         /*
 215          * There is LS1 SoC issue where NOR, FPGA are inaccessible during
 216          * NAND boot because IFC signals > IFC_AD7 are not enabled.
 217          * This workaround changes RCW source to make all signals enabled.
 218          */
 219         porsr1 = in_be32(&gur->porsr1);
 220         pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
 221                  DCFG_CCSR_PORSR1_RCW_SRC_I2C);
 222         out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
 223                  pinctl);
 224 #endif
 225
 226         /* Clear the BSS */
 227         memset(__bss_start, 0, __bss_end - __bss_start);
 228
 229 #ifdef CONFIG_FSL_IFC
 230         init_early_memctl_regs();
 231 #endif
 232
 233         get_clocks();
 234
 235 #if defined(CONFIG_DEEP_SLEEP)
 236         if (is_warm_boot())
 237                 fsl_dp_disable_console();
 238 #endif
 239
 240         preloader_console_init();
 241
 242 #ifdef CONFIG_SPL_I2C_SUPPORT
 243         i2c_init_all();
 244 #endif
 245
 246         major = get_soc_major_rev();
 247         if (major == SOC_MAJOR_VER_1_0)
 248                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 249
 250         dram_init();
 251
 252         /* Allow OCRAM access permission as R/W */
 253 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 254         enable_layerscape_ns_access();
 255 #endif
 256
 257         board_init_r(NULL, 0);
 258 }
 259 #endif
 260
 261 void config_etseccm_source(int etsec_gtx_125_mux)
 262 {
 263         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 264
 265         switch (etsec_gtx_125_mux) {
 266         case GE0_CLK125:
 267                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
 268                 debug("etseccm set to GE0_CLK125\n");
 269                 break;
 270
 271         case GE2_CLK125:
 272                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 273                 debug("etseccm set to GE2_CLK125\n");
 274                 break;
 275
 276         case GE1_CLK125:
 277                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
 278                 debug("etseccm set to GE1_CLK125\n");
 279                 break;
 280
 281         default:
 282                 printf("Error! trying to set etseccm to invalid value\n");
 283                 break;
 284         }
 285 }
 286
 287 int config_board_mux(int ctrl_type)
 288 {
 289         u8 reg12, reg14;
 290
 291         reg12 = QIXIS_READ(brdcfg[12]);
 292         reg14 = QIXIS_READ(brdcfg[14]);
 293
 294         switch (ctrl_type) {
 295         case MUX_TYPE_CAN:
 296                 config_etseccm_source(GE2_CLK125);
 297                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
 298                 break;
 299         case MUX_TYPE_IIC2:
 300                 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
 301                 break;
 302         case MUX_TYPE_RGMII:
 303                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
 304                 break;
 305         case MUX_TYPE_SAI:
 306                 config_etseccm_source(GE2_CLK125);
 307                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
 308                 break;
 309         case MUX_TYPE_SDHC:
 310                 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
 311                 break;
 312         case MUX_TYPE_SD_PCI4:
 313                 reg12 = 0x38;
 314                 break;
 315         case MUX_TYPE_SD_PC_SA_SG_SG:
 316                 reg12 = 0x01;
 317                 break;
 318         case MUX_TYPE_SD_PC_SA_PC_SG:
 319                 reg12 = 0x01;
 320                 break;
 321         case MUX_TYPE_SD_PC_SG_SG:
 322                 reg12 = 0x21;
 323                 break;
 324         default:
 325                 printf("Wrong mux interface type\n");
 326                 return -1;
 327         }
 328
 329         QIXIS_WRITE(brdcfg[12], reg12);
 330         QIXIS_WRITE(brdcfg[14], reg14);
 331
 332         return 0;
 333 }
 334
 335 int config_serdes_mux(void)
 336 {
 337         struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
 338         u32 cfg;
 339
 340         cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 341         cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 342
 343         switch (cfg) {
 344         case 0x0:
 345                 config_board_mux(MUX_TYPE_SD_PCI4);
 346                 break;
 347         case 0x30:
 348                 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
 349                 break;
 350         case 0x60:
 351                 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
 352                 break;
 353         case 0x70:
 354                 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
 355                 break;
 356         default:
 357                 printf("SRDS1 prtcl:0x%x\n", cfg);
 358                 break;
 359         }
 360
 361         return 0;
 362 }
 363
 364 #ifdef CONFIG_BOARD_LATE_INIT
 365 int board_late_init(void)
 366 {
 367 #ifdef CONFIG_SCSI_AHCI_PLAT
 368         ls1021a_sata_init();
 369 #endif
 370 #ifdef CONFIG_CHAIN_OF_TRUST
 371         fsl_setenv_chain_of_trust();
 372 #endif
 373
 374         return 0;
 375 }
 376 #endif
 377
 378 int misc_init_r(void)
 379 {
 380         int conflict_flag;
 381
 382         /* some signals can not enable simultaneous*/
 383         conflict_flag = 0;
 384         if (hwconfig("sdhc"))
 385                 conflict_flag++;
 386         if (hwconfig("iic2"))
 387                 conflict_flag++;
 388         if (conflict_flag > 1) {
 389                 printf("WARNING: pin conflict !\n");
 390                 return 0;
 391         }
 392
 393         conflict_flag = 0;
 394         if (hwconfig("rgmii"))
 395                 conflict_flag++;
 396         if (hwconfig("can"))
 397                 conflict_flag++;
 398         if (hwconfig("sai"))
 399                 conflict_flag++;
 400         if (conflict_flag > 1) {
 401                 printf("WARNING: pin conflict !\n");
 402                 return 0;
 403         }
 404
 405         if (hwconfig("can"))
 406                 config_board_mux(MUX_TYPE_CAN);
 407         else if (hwconfig("rgmii"))
 408                 config_board_mux(MUX_TYPE_RGMII);
 409         else if (hwconfig("sai"))
 410                 config_board_mux(MUX_TYPE_SAI);
 411
 412         if (hwconfig("iic2"))
 413                 config_board_mux(MUX_TYPE_IIC2);
 414         else if (hwconfig("sdhc"))
 415                 config_board_mux(MUX_TYPE_SDHC);
 416
 417 #ifdef CONFIG_FSL_DEVICE_DISABLE
 418         device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 419 #endif
 420 #ifdef CONFIG_FSL_CAAM
 421         return sec_init();
 422 #endif
 423         return 0;
 424 }
 425
 426 int board_init(void)
 427 {
 428         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 429         unsigned int major;
 430
 431 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 432         erratum_a010315();
 433 #endif
 434 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
 435         erratum_a009942_check_cpo();
 436 #endif
 437         major = get_soc_major_rev();
 438         if (major == SOC_MAJOR_VER_1_0) {
 439                 /* Set CCI-400 control override register to
 440                  * enable barrier transaction */
 441                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 442         }
 443
 444         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 445
 446 #ifndef CONFIG_SYS_FSL_NO_SERDES
 447         fsl_serdes_init();
 448         config_serdes_mux();
 449 #endif
 450
 451         ls102xa_smmu_stream_id_init();
 452
 453 #ifdef CONFIG_U_QE
 454         u_qe_init();
 455 #endif
 456
 457         return 0;
 458 }
 459
 460 #if defined(CONFIG_DEEP_SLEEP)
 461 void board_sleep_prepare(void)
 462 {
 463         struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
 464         unsigned int major;
 465
 466         major = get_soc_major_rev();
 467         if (major == SOC_MAJOR_VER_1_0) {
 468                 /* Set CCI-400 control override register to
 469                  * enable barrier transaction */
 470                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 471         }
 472
 473
 474 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 475         enable_layerscape_ns_access();
 476 #endif
 477 }
 478 #endif
 479
 480 int ft_board_setup(void *blob, bd_t *bd)
 481 {
 482         ft_cpu_setup(blob, bd);
 483
 484 #ifdef CONFIG_PCI
 485         ft_pci_setup(blob, bd);
 486 #endif
 487
 488         return 0;
 489 }
 490
 491 u8 flash_read8(void *addr)
 492 {
 493         return __raw_readb(addr + 1);
 494 }
 495
 496 void flash_write16(u16 val, void *addr)
 497 {
 498         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 499
 500         __raw_writew(shftval, addr);
 501 }
 502
 503 u16 flash_read16(void *addr)
 504 {
 505         u16 val = __raw_readw(addr);
 506
 507         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 508 }