2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/ls102xa_stream_id.h>
14 #include <asm/arch/ls102xa_devdis.h>
15 #include <asm/arch/ls102xa_soc.h>
16 #include <asm/arch/ls102xa_sata.h>
20 #include <fsl_esdhc.h>
22 #include <fsl_immap.h>
27 #include <fsl_devdis.h>
29 #include "../common/sleep.h"
31 #include "../../../drivers/qe/qe.h"
35 DECLARE_GLOBAL_DATA_PTR
;
37 #define VERSION_MASK 0x00FF
38 #define BANK_MASK 0x0001
39 #define CONFIG_RESET 0x1
40 #define INIT_RESET 0x1
42 #define CPLD_SET_MUX_SERDES 0x20
43 #define CPLD_SET_BOOT_BANK 0x40
45 #define BOOT_FROM_UPPER_BANK 0x0
46 #define BOOT_FROM_LOWER_BANK 0x1
48 #define LANEB_SATA (0x01)
49 #define LANEB_SGMII1 (0x02)
50 #define LANEC_SGMII1 (0x04)
51 #define LANEC_PCIEX1 (0x08)
52 #define LANED_PCIEX2 (0x10)
53 #define LANED_SGMII2 (0x20)
55 #define MASK_LANE_B 0x1
56 #define MASK_LANE_C 0x2
57 #define MASK_LANE_D 0x4
58 #define MASK_SGMII 0x8
60 #define KEEP_STATUS 0x0
61 #define NEED_RESET 0x1
63 #define SOFT_MUX_ON_I2C3_IFC 0x2
64 #define SOFT_MUX_ON_CAN3_USB2 0x8
65 #define SOFT_MUX_ON_QE_LCD 0x10
67 #define PIN_I2C3_IFC_MUX_I2C3 0x0
68 #define PIN_I2C3_IFC_MUX_IFC 0x1
69 #define PIN_CAN3_USB2_MUX_USB2 0x0
70 #define PIN_CAN3_USB2_MUX_CAN3 0x1
71 #define PIN_QE_LCD_MUX_LCD 0x0
72 #define PIN_QE_LCD_MUX_QE 0x1
75 u8 cpld_ver
; /* cpld revision */
76 u8 cpld_ver_sub
; /* cpld sub revision */
77 u8 pcba_ver
; /* pcb revision number */
78 u8 system_rst
; /* reset system by cpld */
79 u8 soft_mux_on
; /* CPLD override physical switches Enable */
80 u8 cfg_rcw_src1
; /* Reset config word 1 */
81 u8 cfg_rcw_src2
; /* Reset config word 2 */
82 u8 vbank
; /* Flash bank selection Control */
83 u8 gpio
; /* GPIO for TWR-ELEV */
86 u8 can3_usb2_mux
; /* CAN3 and USB2 Selection */
87 u8 qe_lcd_mux
; /* QE and LCD Selection */
88 u8 serdes_mux
; /* Multiplexed pins for SerDes Lanes */
89 u8 global_rst
; /* reset with init CPLD reg to default */
90 u8 rev1
; /* Reserved */
91 u8 rev2
; /* Reserved */
94 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
95 static void convert_serdes_mux(int type
, int need_reset
);
99 struct cpld_data
*cpld_data
= (void *)(CONFIG_SYS_CPLD_BASE
);
101 printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n",
102 in_8(&cpld_data
->cpld_ver
) & VERSION_MASK
,
103 in_8(&cpld_data
->cpld_ver_sub
) & VERSION_MASK
,
104 in_8(&cpld_data
->pcba_ver
) & VERSION_MASK
,
105 in_8(&cpld_data
->vbank
) & BANK_MASK
);
108 printf("soft_mux_on =%x\n",
109 in_8(&cpld_data
->soft_mux_on
));
110 printf("cfg_rcw_src1 =%x\n",
111 in_8(&cpld_data
->cfg_rcw_src1
));
112 printf("cfg_rcw_src2 =%x\n",
113 in_8(&cpld_data
->cfg_rcw_src2
));
114 printf("vbank =%x\n",
115 in_8(&cpld_data
->vbank
));
117 in_8(&cpld_data
->gpio
));
118 printf("i2c3_ifc_mux =%x\n",
119 in_8(&cpld_data
->i2c3_ifc_mux
));
120 printf("mux_spi2 =%x\n",
121 in_8(&cpld_data
->mux_spi2
));
122 printf("can3_usb2_mux =%x\n",
123 in_8(&cpld_data
->can3_usb2_mux
));
124 printf("qe_lcd_mux =%x\n",
125 in_8(&cpld_data
->qe_lcd_mux
));
126 printf("serdes_mux =%x\n",
127 in_8(&cpld_data
->serdes_mux
));
134 puts("Board: LS1021ATWR\n");
135 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
142 void ddrmc_init(void)
144 struct ccsr_ddr
*ddr
= (struct ccsr_ddr
*)CONFIG_SYS_FSL_DDR_ADDR
;
147 out_be32(&ddr
->sdram_cfg
, DDR_SDRAM_CFG
);
149 out_be32(&ddr
->cs0_bnds
, DDR_CS0_BNDS
);
150 out_be32(&ddr
->cs0_config
, DDR_CS0_CONFIG
);
152 out_be32(&ddr
->timing_cfg_0
, DDR_TIMING_CFG_0
);
153 out_be32(&ddr
->timing_cfg_1
, DDR_TIMING_CFG_1
);
154 out_be32(&ddr
->timing_cfg_2
, DDR_TIMING_CFG_2
);
155 out_be32(&ddr
->timing_cfg_3
, DDR_TIMING_CFG_3
);
156 out_be32(&ddr
->timing_cfg_4
, DDR_TIMING_CFG_4
);
157 out_be32(&ddr
->timing_cfg_5
, DDR_TIMING_CFG_5
);
159 #ifdef CONFIG_DEEP_SLEEP
160 if (is_warm_boot()) {
161 out_be32(&ddr
->sdram_cfg_2
,
162 DDR_SDRAM_CFG_2
& ~SDRAM_CFG2_D_INIT
);
163 out_be32(&ddr
->init_addr
, CONFIG_SYS_SDRAM_BASE
);
164 out_be32(&ddr
->init_ext_addr
, (1 << 31));
166 /* DRAM VRef will not be trained */
167 out_be32(&ddr
->ddr_cdr2
,
168 DDR_DDR_CDR2
& ~DDR_CDR2_VREF_TRAIN_EN
);
172 out_be32(&ddr
->sdram_cfg_2
, DDR_SDRAM_CFG_2
);
173 out_be32(&ddr
->ddr_cdr2
, DDR_DDR_CDR2
);
176 out_be32(&ddr
->sdram_mode
, DDR_SDRAM_MODE
);
177 out_be32(&ddr
->sdram_mode_2
, DDR_SDRAM_MODE_2
);
179 out_be32(&ddr
->sdram_interval
, DDR_SDRAM_INTERVAL
);
181 out_be32(&ddr
->ddr_wrlvl_cntl
, DDR_DDR_WRLVL_CNTL
);
183 out_be32(&ddr
->ddr_wrlvl_cntl_2
, DDR_DDR_WRLVL_CNTL_2
);
184 out_be32(&ddr
->ddr_wrlvl_cntl_3
, DDR_DDR_WRLVL_CNTL_3
);
186 out_be32(&ddr
->ddr_cdr1
, DDR_DDR_CDR1
);
188 out_be32(&ddr
->sdram_clk_cntl
, DDR_SDRAM_CLK_CNTL
);
189 out_be32(&ddr
->ddr_zq_cntl
, DDR_DDR_ZQ_CNTL
);
191 out_be32(&ddr
->cs0_config_2
, DDR_CS0_CONFIG_2
);
194 #ifdef CONFIG_DEEP_SLEEP
195 if (is_warm_boot()) {
196 /* enter self-refresh */
197 temp_sdram_cfg
= in_be32(&ddr
->sdram_cfg_2
);
198 temp_sdram_cfg
|= SDRAM_CFG2_FRC_SR
;
199 out_be32(&ddr
->sdram_cfg_2
, temp_sdram_cfg
);
201 temp_sdram_cfg
= (DDR_SDRAM_CFG_MEM_EN
| SDRAM_CFG_BI
);
204 temp_sdram_cfg
= (DDR_SDRAM_CFG_MEM_EN
& ~SDRAM_CFG_BI
);
206 out_be32(&ddr
->sdram_cfg
, DDR_SDRAM_CFG
| temp_sdram_cfg
);
208 #ifdef CONFIG_DEEP_SLEEP
209 if (is_warm_boot()) {
210 /* exit self-refresh */
211 temp_sdram_cfg
= in_be32(&ddr
->sdram_cfg_2
);
212 temp_sdram_cfg
&= ~SDRAM_CFG2_FRC_SR
;
213 out_be32(&ddr
->sdram_cfg_2
, temp_sdram_cfg
);
220 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
224 gd
->ram_size
= get_ram_size((void *)PHYS_SDRAM
, PHYS_SDRAM_SIZE
);
226 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
233 #ifdef CONFIG_FSL_ESDHC
234 struct fsl_esdhc_cfg esdhc_cfg
[1] = {
235 {CONFIG_SYS_FSL_ESDHC_ADDR
},
238 int board_mmc_init(bd_t
*bis
)
240 esdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC_CLK
);
242 return fsl_esdhc_initialize(bis
, &esdhc_cfg
[0]);
246 #ifdef CONFIG_TSEC_ENET
247 int board_eth_init(bd_t
*bis
)
249 struct fsl_pq_mdio_info mdio_info
;
250 struct tsec_info_struct tsec_info
[4];
254 SET_STD_TSEC_INFO(tsec_info
[num
], 1);
255 if (is_serdes_configured(SGMII_TSEC1
)) {
256 puts("eTSEC1 is in sgmii mode.\n");
257 tsec_info
[num
].flags
|= TSEC_SGMII
;
262 SET_STD_TSEC_INFO(tsec_info
[num
], 2);
263 if (is_serdes_configured(SGMII_TSEC2
)) {
264 puts("eTSEC2 is in sgmii mode.\n");
265 tsec_info
[num
].flags
|= TSEC_SGMII
;
270 SET_STD_TSEC_INFO(tsec_info
[num
], 3);
274 printf("No TSECs initialized\n");
278 mdio_info
.regs
= (struct tsec_mii_mng
*)CONFIG_SYS_MDIO_BASE_ADDR
;
279 mdio_info
.name
= DEFAULT_MII_NAME
;
280 fsl_pq_mdio_init(bis
, &mdio_info
);
282 tsec_eth_init(bis
, tsec_info
, num
);
284 return pci_eth_init(bis
);
288 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
289 int config_serdes_mux(void)
291 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
292 u32 protocol
= in_be32(&gur
->rcwsr
[4]) & RCWSR4_SRDS1_PRTCL_MASK
;
294 protocol
>>= RCWSR4_SRDS1_PRTCL_SHIFT
;
297 convert_serdes_mux(LANEB_SATA
, KEEP_STATUS
);
298 convert_serdes_mux(LANED_PCIEX2
|
299 LANEC_PCIEX1
, KEEP_STATUS
);
302 convert_serdes_mux(LANEB_SGMII1
, KEEP_STATUS
);
303 convert_serdes_mux(LANEC_PCIEX1
, KEEP_STATUS
);
304 convert_serdes_mux(LANED_SGMII2
, KEEP_STATUS
);
307 convert_serdes_mux(LANEB_SATA
, KEEP_STATUS
);
308 convert_serdes_mux(LANEC_SGMII1
, KEEP_STATUS
);
309 convert_serdes_mux(LANED_SGMII2
, KEEP_STATUS
);
312 convert_serdes_mux(LANEB_SATA
, KEEP_STATUS
);
313 convert_serdes_mux(LANEC_PCIEX1
, KEEP_STATUS
);
314 convert_serdes_mux(LANED_SGMII2
, KEEP_STATUS
);
322 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
323 int config_board_mux(void)
325 struct cpld_data
*cpld_data
= (void *)(CONFIG_SYS_CPLD_BASE
);
329 if (hwconfig("i2c3")) {
331 cpld_data
->soft_mux_on
|= SOFT_MUX_ON_I2C3_IFC
;
332 cpld_data
->i2c3_ifc_mux
= PIN_I2C3_IFC_MUX_I2C3
;
335 if (hwconfig("ifc")) {
337 /* some signals can not enable simultaneous*/
338 if (conflict_flag
> 1)
340 cpld_data
->soft_mux_on
|= SOFT_MUX_ON_I2C3_IFC
;
341 cpld_data
->i2c3_ifc_mux
= PIN_I2C3_IFC_MUX_IFC
;
345 if (hwconfig("usb2")) {
347 cpld_data
->soft_mux_on
|= SOFT_MUX_ON_CAN3_USB2
;
348 cpld_data
->can3_usb2_mux
= PIN_CAN3_USB2_MUX_USB2
;
351 if (hwconfig("can3")) {
353 /* some signals can not enable simultaneous*/
354 if (conflict_flag
> 1)
356 cpld_data
->soft_mux_on
|= SOFT_MUX_ON_CAN3_USB2
;
357 cpld_data
->can3_usb2_mux
= PIN_CAN3_USB2_MUX_CAN3
;
361 if (hwconfig("lcd")) {
363 cpld_data
->soft_mux_on
|= SOFT_MUX_ON_QE_LCD
;
364 cpld_data
->qe_lcd_mux
= PIN_QE_LCD_MUX_LCD
;
367 if (hwconfig("qe")) {
369 /* some signals can not enable simultaneous*/
370 if (conflict_flag
> 1)
372 cpld_data
->soft_mux_on
|= SOFT_MUX_ON_QE_LCD
;
373 cpld_data
->qe_lcd_mux
= PIN_QE_LCD_MUX_QE
;
379 printf("WARNING: pin conflict! MUX setting may failed!\n");
384 int board_early_init_f(void)
386 struct ccsr_scfg
*scfg
= (struct ccsr_scfg
*)CONFIG_SYS_FSL_SCFG_ADDR
;
388 #ifdef CONFIG_TSEC_ENET
389 /* clear BD & FR bits for BE BD's and frame data */
390 clrbits_be32(&scfg
->etsecdmamcr
, SCFG_ETSECDMAMCR_LE_BD_FR
);
391 out_be32(&scfg
->etsecmcr
, SCFG_ETSECCMCR_GE2_CLK125
);
394 #ifdef CONFIG_FSL_IFC
395 init_early_memctl_regs();
400 #if defined(CONFIG_DEEP_SLEEP)
401 if (is_warm_boot()) {
410 #ifdef CONFIG_SPL_BUILD
411 void board_init_f(ulong dummy
)
413 void (*second_uboot
)(void);
416 memset(__bss_start
, 0, __bss_end
- __bss_start
);
420 #if defined(CONFIG_DEEP_SLEEP)
422 fsl_dp_disable_console();
425 preloader_console_init();
429 /* Allow OCRAM access permission as R/W */
430 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
431 enable_layerscape_ns_access();
432 enable_layerscape_ns_access();
436 * if it is woken up from deep sleep, then jump to second
437 * stage uboot and continue executing without recopying
438 * it from SD since it has already been reserved in memeory
441 if (is_warm_boot()) {
442 second_uboot
= (void (*)(void))CONFIG_SYS_TEXT_BASE
;
446 board_init_r(NULL
, 0);
451 struct liodn_id_table sec_liodn_tbl
[] = {
452 SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
453 SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
454 SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
455 SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
456 SET_SEC_RTIC_LIODN_ENTRY(a
, 0x10),
457 SET_SEC_RTIC_LIODN_ENTRY(b
, 0x10),
458 SET_SEC_RTIC_LIODN_ENTRY(c
, 0x10),
459 SET_SEC_RTIC_LIODN_ENTRY(d
, 0x10),
460 SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
461 SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
462 SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
463 SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
464 SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
465 SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
466 SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
467 SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
470 struct smmu_stream_id dev_stream_id
[] = {
471 { 0x100, 0x01, "ETSEC MAC1" },
472 { 0x104, 0x02, "ETSEC MAC2" },
473 { 0x108, 0x03, "ETSEC MAC3" },
474 { 0x10c, 0x04, "PEX1" },
475 { 0x110, 0x05, "PEX2" },
476 { 0x114, 0x06, "qDMA" },
477 { 0x118, 0x07, "SATA" },
478 { 0x11c, 0x08, "USB3" },
479 { 0x120, 0x09, "QE" },
480 { 0x124, 0x0a, "eSDHC" },
481 { 0x128, 0x0b, "eMA" },
482 { 0x14c, 0x0c, "2D-ACE" },
483 { 0x150, 0x0d, "USB2" },
484 { 0x18c, 0x0e, "DEBUG" },
487 #ifdef CONFIG_DEEP_SLEEP
488 /* program the regulator (MC34VR500) to support deep sleep */
489 void ls1twr_program_regulator(void)
491 unsigned int i2c_bus
;
494 #define LS1TWR_I2C_BUS_MC34VR500 1
495 #define MC34VR500_ADDR 0x8
496 #define MC34VR500_DEVICEID 0x4
497 #define MC34VR500_DEVICEID_MASK 0x0f
499 i2c_bus
= i2c_get_bus_num();
500 i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500
);
501 i2c_device_id
= i2c_reg_read(MC34VR500_ADDR
, 0x0) &
502 MC34VR500_DEVICEID_MASK
;
503 if (i2c_device_id
!= MC34VR500_DEVICEID
) {
504 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
508 i2c_reg_write(MC34VR500_ADDR
, 0x31, 0x4);
509 i2c_reg_write(MC34VR500_ADDR
, 0x4d, 0x4);
510 i2c_reg_write(MC34VR500_ADDR
, 0x6d, 0x38);
511 i2c_reg_write(MC34VR500_ADDR
, 0x6f, 0x37);
512 i2c_reg_write(MC34VR500_ADDR
, 0x71, 0x30);
514 i2c_set_bus_num(i2c_bus
);
520 #ifndef CONFIG_SYS_FSL_NO_SERDES
522 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
527 ls1021x_config_caam_stream_id(sec_liodn_tbl
,
528 ARRAY_SIZE(sec_liodn_tbl
));
529 ls102xa_config_smmu_stream_id(dev_stream_id
,
530 ARRAY_SIZE(dev_stream_id
));
532 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
533 enable_layerscape_ns_access();
540 #ifdef CONFIG_DEEP_SLEEP
541 ls1twr_program_regulator();
546 #ifdef CONFIG_BOARD_LATE_INIT
547 int board_late_init(void)
549 #ifdef CONFIG_SCSI_AHCI_PLAT
557 #if defined(CONFIG_MISC_INIT_R)
558 int misc_init_r(void)
560 #ifdef CONFIG_FSL_DEVICE_DISABLE
561 device_disable(devdis_tbl
, ARRAY_SIZE(devdis_tbl
));
563 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
567 #ifdef CONFIG_FSL_CAAM
573 #if defined(CONFIG_DEEP_SLEEP)
574 void board_sleep_prepare(void)
576 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
577 enable_layerscape_ns_access();
582 int ft_board_setup(void *blob
, bd_t
*bd
)
584 ft_cpu_setup(blob
, bd
);
587 ft_pci_setup(blob
, bd
);
593 u8
flash_read8(void *addr
)
595 return __raw_readb(addr
+ 1);
598 void flash_write16(u16 val
, void *addr
)
600 u16 shftval
= (((val
>> 8) & 0xff) | ((val
<< 8) & 0xff00));
602 __raw_writew(shftval
, addr
);
605 u16
flash_read16(void *addr
)
607 u16 val
= __raw_readw(addr
);
609 return (((val
) >> 8) & 0x00ff) | (((val
) << 8) & 0xff00);
612 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
613 static void convert_flash_bank(char bank
)
615 struct cpld_data
*cpld_data
= (void *)(CONFIG_SYS_CPLD_BASE
);
617 printf("Now switch to boot from flash bank %d.\n", bank
);
618 cpld_data
->soft_mux_on
= CPLD_SET_BOOT_BANK
;
619 cpld_data
->vbank
= bank
;
621 printf("Reset board to enable configuration.\n");
622 cpld_data
->system_rst
= CONFIG_RESET
;
625 static int flash_bank_cmd(cmd_tbl_t
*cmdtp
, int flag
, int argc
,
629 return CMD_RET_USAGE
;
630 if (strcmp(argv
[1], "0") == 0)
631 convert_flash_bank(BOOT_FROM_UPPER_BANK
);
632 else if (strcmp(argv
[1], "1") == 0)
633 convert_flash_bank(BOOT_FROM_LOWER_BANK
);
635 return CMD_RET_USAGE
;
641 boot_bank
, 2, 0, flash_bank_cmd
,
642 "Flash bank Selection Control",
643 "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
646 static int cpld_reset_cmd(cmd_tbl_t
*cmdtp
, int flag
, int argc
,
649 struct cpld_data
*cpld_data
= (void *)(CONFIG_SYS_CPLD_BASE
);
652 return CMD_RET_USAGE
;
653 if ((argc
== 1) || (strcmp(argv
[1], "conf") == 0))
654 cpld_data
->system_rst
= CONFIG_RESET
;
655 else if (strcmp(argv
[1], "init") == 0)
656 cpld_data
->global_rst
= INIT_RESET
;
658 return CMD_RET_USAGE
;
664 cpld_reset
, 2, 0, cpld_reset_cmd
,
667 " -reset with current CPLD configuration\n"
669 " -reset and initial CPLD configuration with default value"
673 static void convert_serdes_mux(int type
, int need_reset
)
676 struct cpld_data
*cpld_data
= (void *)(CONFIG_SYS_CPLD_BASE
);
678 current_serdes
= cpld_data
->serdes_mux
;
682 current_serdes
&= ~MASK_LANE_B
;
685 current_serdes
|= (MASK_LANE_B
| MASK_SGMII
| MASK_LANE_C
);
688 current_serdes
&= ~(MASK_LANE_B
| MASK_SGMII
| MASK_LANE_C
);
691 current_serdes
|= MASK_LANE_D
;
694 current_serdes
|= MASK_LANE_C
;
696 case (LANED_PCIEX2
| LANEC_PCIEX1
):
697 current_serdes
|= MASK_LANE_C
;
698 current_serdes
&= ~MASK_LANE_D
;
701 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type
);
705 cpld_data
->soft_mux_on
|= CPLD_SET_MUX_SERDES
;
706 cpld_data
->serdes_mux
= current_serdes
;
708 if (need_reset
== 1) {
709 printf("Reset board to enable configuration\n");
710 cpld_data
->system_rst
= CONFIG_RESET
;
714 void print_serdes_mux(void)
717 struct cpld_data
*cpld_data
= (void *)(CONFIG_SYS_CPLD_BASE
);
719 current_serdes
= cpld_data
->serdes_mux
;
721 printf("Serdes Lane B: ");
722 if ((current_serdes
& MASK_LANE_B
) == 0)
725 printf("SGMII 1,\n");
727 printf("Serdes Lane C: ");
728 if ((current_serdes
& MASK_LANE_C
) == 0)
729 printf("SGMII 1,\n");
733 printf("Serdes Lane D: ");
734 if ((current_serdes
& MASK_LANE_D
) == 0)
737 printf("SGMII 2,\n");
739 printf("SGMII 1 is on lane ");
740 if ((current_serdes
& MASK_SGMII
) == 0)
746 static int serdes_mux_cmd(cmd_tbl_t
*cmdtp
, int flag
, int argc
,
750 return CMD_RET_USAGE
;
751 if (strcmp(argv
[1], "sata") == 0) {
752 printf("Set serdes lane B to SATA.\n");
753 convert_serdes_mux(LANEB_SATA
, NEED_RESET
);
754 } else if (strcmp(argv
[1], "sgmii1b") == 0) {
755 printf("Set serdes lane B to SGMII 1.\n");
756 convert_serdes_mux(LANEB_SGMII1
, NEED_RESET
);
757 } else if (strcmp(argv
[1], "sgmii1c") == 0) {
758 printf("Set serdes lane C to SGMII 1.\n");
759 convert_serdes_mux(LANEC_SGMII1
, NEED_RESET
);
760 } else if (strcmp(argv
[1], "sgmii2") == 0) {
761 printf("Set serdes lane D to SGMII 2.\n");
762 convert_serdes_mux(LANED_SGMII2
, NEED_RESET
);
763 } else if (strcmp(argv
[1], "pciex1") == 0) {
764 printf("Set serdes lane C to PCIe X1.\n");
765 convert_serdes_mux(LANEC_PCIEX1
, NEED_RESET
);
766 } else if (strcmp(argv
[1], "pciex2") == 0) {
767 printf("Set serdes lane C & lane D to PCIe X2.\n");
768 convert_serdes_mux((LANED_PCIEX2
| LANEC_PCIEX1
), NEED_RESET
);
769 } else if (strcmp(argv
[1], "show") == 0) {
772 return CMD_RET_USAGE
;
779 lane_bank
, 2, 0, serdes_mux_cmd
,
780 "Multiplexed function setting for SerDes Lanes",
782 " -change lane B to sata\n"
783 "lane_bank sgmii1b\n"
784 " -change lane B to SGMII1\n"
785 "lane_bank sgmii1c\n"
786 " -change lane C to SGMII1\n"
788 " -change lane D to SGMII2\n"
790 " -change lane C to PCIeX1\n"
792 " -change lane C & lane D to PCIeX2\n"
793 "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"