2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <fsl_ddr_sdram.h>
9 #include <fsl_ddr_dimm_params.h>
11 #ifdef CONFIG_FSL_DEEP_SLEEP
12 #include <fsl_sleep.h>
15 DECLARE_GLOBAL_DATA_PTR
;
17 void fsl_ddr_board_options(memctl_options_t
*popts
,
19 unsigned int ctrl_num
)
21 const struct board_specific_parameters
*pbsp
, *pbsp_highest
= NULL
;
25 printf("Not supported controller number %d\n", ctrl_num
);
33 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
34 * freqency and n_banks specified in board_specific_parameters table.
36 ddr_freq
= get_ddr_freq(0) / 1000000;
37 while (pbsp
->datarate_mhz_high
) {
38 if (pbsp
->n_ranks
== pdimm
->n_ranks
) {
39 if (ddr_freq
<= pbsp
->datarate_mhz_high
) {
40 popts
->clk_adjust
= pbsp
->clk_adjust
;
41 popts
->wrlvl_start
= pbsp
->wrlvl_start
;
42 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
43 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
44 popts
->cpo_override
= pbsp
->cpo_override
;
45 popts
->write_data_delay
=
46 pbsp
->write_data_delay
;
55 printf("Error: board specific timing not found for %lu MT/s\n",
57 printf("Trying to use the highest speed (%u) parameters\n",
58 pbsp_highest
->datarate_mhz_high
);
59 popts
->clk_adjust
= pbsp_highest
->clk_adjust
;
60 popts
->wrlvl_start
= pbsp_highest
->wrlvl_start
;
61 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
62 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
64 panic("DIMM is not supported by this board");
67 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
68 pbsp
->n_ranks
, pbsp
->datarate_mhz_high
, pbsp
->rank_gb
);
70 /* force DDR bus width to 32 bits */
71 popts
->data_bus_width
= 1;
72 popts
->otf_burst_chop_en
= 0;
73 popts
->burst_length
= DDR_BL8
;
76 * Factors to consider for half-strength driver enable:
77 * - number of DIMMs installed
79 popts
->half_strength_driver_enable
= 1;
81 * Write leveling override
83 popts
->wrlvl_override
= 1;
84 popts
->wrlvl_sample
= 0xf;
87 * Rtt and Rtt_WR override
89 popts
->rtt_override
= 0;
91 /* Enable ZQ calibration */
94 popts
->ddr_cdr1
= DDR_CDR1_DHC_EN
| DDR_CDR1_ODT(DDR_CDR_ODT_80ohm
);
95 popts
->ddr_cdr2
= DDR_CDR2_ODT(DDR_CDR_ODT_80ohm
) |
96 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
99 /* DDR model number: MT40A512M8HX-093E */
100 #ifdef CONFIG_SYS_DDR_RAW_TIMING
101 dimm_params_t ddr_raw_timing
= {
103 .rank_density
= 2147483648u,
104 .capacity
= 2147483648u,
105 .primary_sdram_width
= 32,
107 .registered_dimm
= 0,
112 .bank_group_bits
= 2,
114 .burst_lengths_bitmask
= 0x0c,
118 .caslat_x
= 0x000DFA00,
131 .refresh_rate_ps
= 7800000,
132 .dq_mapping
[0] = 0x0,
133 .dq_mapping
[1] = 0x0,
134 .dq_mapping
[2] = 0x0,
135 .dq_mapping
[3] = 0x0,
136 .dq_mapping
[4] = 0x0,
137 .dq_mapping
[5] = 0x0,
138 .dq_mapping
[6] = 0x0,
139 .dq_mapping
[7] = 0x0,
140 .dq_mapping
[8] = 0x0,
141 .dq_mapping
[9] = 0x0,
142 .dq_mapping
[10] = 0x0,
143 .dq_mapping
[11] = 0x0,
144 .dq_mapping
[12] = 0x0,
145 .dq_mapping
[13] = 0x0,
146 .dq_mapping
[14] = 0x0,
147 .dq_mapping
[15] = 0x0,
148 .dq_mapping
[16] = 0x0,
149 .dq_mapping
[17] = 0x0,
153 int fsl_ddr_get_dimm_params(dimm_params_t
*pdimm
,
154 unsigned int controller_number
,
155 unsigned int dimm_number
)
157 static const char dimm_model
[] = "Fixed DDR on board";
159 if (((controller_number
== 0) && (dimm_number
== 0)) ||
160 ((controller_number
== 1) && (dimm_number
== 0))) {
161 memcpy(pdimm
, &ddr_raw_timing
, sizeof(dimm_params_t
));
162 memset(pdimm
->mpart
, 0, sizeof(pdimm
->mpart
));
163 memcpy(pdimm
->mpart
, dimm_model
, sizeof(dimm_model
) - 1);
170 phys_size_t
initdram(int board_type
)
172 phys_size_t dram_size
;
174 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
175 puts("Initializing DDR....\n");
176 dram_size
= fsl_ddr_sdram();
178 dram_size
= fsl_ddr_sdram_size();
180 #ifdef CONFIG_FSL_DEEP_SLEEP
181 fsl_dp_ddr_restore();
187 void dram_init_banksize(void)
190 * gd->secure_ram tracks the location of secure memory.
191 * It was set as if the memory starts from 0.
192 * The address needs to add the offset of its bank.
194 gd
->bd
->bi_dram
[0].start
= CONFIG_SYS_SDRAM_BASE
;
195 if (gd
->ram_size
> CONFIG_SYS_DDR_BLOCK1_SIZE
) {
196 gd
->bd
->bi_dram
[0].size
= CONFIG_SYS_DDR_BLOCK1_SIZE
;
197 gd
->bd
->bi_dram
[1].start
= CONFIG_SYS_DDR_BLOCK2_BASE
;
198 gd
->bd
->bi_dram
[1].size
= gd
->ram_size
-
199 CONFIG_SYS_DDR_BLOCK1_SIZE
;
200 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
201 gd
->secure_ram
= gd
->bd
->bi_dram
[1].start
+
203 CONFIG_SYS_DDR_BLOCK1_SIZE
;
204 gd
->secure_ram
|= MEM_RESERVE_SECURE_MAINTAINED
;
207 gd
->bd
->bi_dram
[0].size
= gd
->ram_size
;
208 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
209 gd
->secure_ram
= gd
->bd
->bi_dram
[0].start
+ gd
->secure_ram
;
210 gd
->secure_ram
|= MEM_RESERVE_SECURE_MAINTAINED
;