2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <fsl_ddr_sdram.h>
9 #include <fsl_ddr_dimm_params.h>
11 #ifdef CONFIG_FSL_DEEP_SLEEP
12 #include <fsl_sleep.h>
14 #include <asm/arch/clock.h>
16 DECLARE_GLOBAL_DATA_PTR
;
18 void fsl_ddr_board_options(memctl_options_t
*popts
,
20 unsigned int ctrl_num
)
22 const struct board_specific_parameters
*pbsp
, *pbsp_highest
= NULL
;
26 printf("Not supported controller number %d\n", ctrl_num
);
34 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
35 * freqency and n_banks specified in board_specific_parameters table.
37 ddr_freq
= get_ddr_freq(0) / 1000000;
38 while (pbsp
->datarate_mhz_high
) {
39 if (pbsp
->n_ranks
== pdimm
->n_ranks
) {
40 if (ddr_freq
<= pbsp
->datarate_mhz_high
) {
41 popts
->clk_adjust
= pbsp
->clk_adjust
;
42 popts
->wrlvl_start
= pbsp
->wrlvl_start
;
43 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
44 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
45 popts
->cpo_override
= pbsp
->cpo_override
;
46 popts
->write_data_delay
=
47 pbsp
->write_data_delay
;
56 printf("Error: board specific timing not found for %lu MT/s\n",
58 printf("Trying to use the highest speed (%u) parameters\n",
59 pbsp_highest
->datarate_mhz_high
);
60 popts
->clk_adjust
= pbsp_highest
->clk_adjust
;
61 popts
->wrlvl_start
= pbsp_highest
->wrlvl_start
;
62 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
63 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
65 panic("DIMM is not supported by this board");
68 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
69 pbsp
->n_ranks
, pbsp
->datarate_mhz_high
, pbsp
->rank_gb
);
71 /* force DDR bus width to 32 bits */
72 popts
->data_bus_width
= 1;
73 popts
->otf_burst_chop_en
= 0;
74 popts
->burst_length
= DDR_BL8
;
77 * Factors to consider for half-strength driver enable:
78 * - number of DIMMs installed
80 popts
->half_strength_driver_enable
= 1;
82 * Write leveling override
84 popts
->wrlvl_override
= 1;
85 popts
->wrlvl_sample
= 0xf;
88 * Rtt and Rtt_WR override
90 popts
->rtt_override
= 0;
92 /* Enable ZQ calibration */
95 /* optimize cpo for erratum A-009942 */
96 popts
->cpo_sample
= 0x46;
98 popts
->ddr_cdr1
= DDR_CDR1_DHC_EN
| DDR_CDR1_ODT(DDR_CDR_ODT_80ohm
);
99 popts
->ddr_cdr2
= DDR_CDR2_ODT(DDR_CDR_ODT_80ohm
) |
100 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
103 /* DDR model number: MT40A512M8HX-093E */
104 #ifdef CONFIG_SYS_DDR_RAW_TIMING
105 dimm_params_t ddr_raw_timing
= {
107 .rank_density
= 2147483648u,
108 .capacity
= 2147483648u,
109 .primary_sdram_width
= 32,
111 .registered_dimm
= 0,
116 .bank_group_bits
= 2,
118 .burst_lengths_bitmask
= 0x0c,
122 .caslat_x
= 0x000DFA00,
135 .refresh_rate_ps
= 7800000,
136 .dq_mapping
[0] = 0x0,
137 .dq_mapping
[1] = 0x0,
138 .dq_mapping
[2] = 0x0,
139 .dq_mapping
[3] = 0x0,
140 .dq_mapping
[4] = 0x0,
141 .dq_mapping
[5] = 0x0,
142 .dq_mapping
[6] = 0x0,
143 .dq_mapping
[7] = 0x0,
144 .dq_mapping
[8] = 0x0,
145 .dq_mapping
[9] = 0x0,
146 .dq_mapping
[10] = 0x0,
147 .dq_mapping
[11] = 0x0,
148 .dq_mapping
[12] = 0x0,
149 .dq_mapping
[13] = 0x0,
150 .dq_mapping
[14] = 0x0,
151 .dq_mapping
[15] = 0x0,
152 .dq_mapping
[16] = 0x0,
153 .dq_mapping
[17] = 0x0,
157 int fsl_ddr_get_dimm_params(dimm_params_t
*pdimm
,
158 unsigned int controller_number
,
159 unsigned int dimm_number
)
161 static const char dimm_model
[] = "Fixed DDR on board";
163 if (((controller_number
== 0) && (dimm_number
== 0)) ||
164 ((controller_number
== 1) && (dimm_number
== 0))) {
165 memcpy(pdimm
, &ddr_raw_timing
, sizeof(dimm_params_t
));
166 memset(pdimm
->mpart
, 0, sizeof(pdimm
->mpart
));
167 memcpy(pdimm
->mpart
, dimm_model
, sizeof(dimm_model
) - 1);
174 phys_size_t
fixed_sdram(void)
178 fsl_ddr_cfg_regs_t ddr_cfg_regs
;
179 phys_size_t ddr_size
;
180 ulong ddr_freq
, ddr_freq_mhz
;
182 ddr_freq
= get_ddr_freq(0);
183 ddr_freq_mhz
= ddr_freq
/ 1000000;
185 printf("Configuring DDR for %s MT/s data rate\n",
186 strmhz(buf
, ddr_freq
));
188 for (i
= 0; fixed_ddr_parm_0
[i
].max_freq
> 0; i
++) {
189 if ((ddr_freq_mhz
> fixed_ddr_parm_0
[i
].min_freq
) &&
190 (ddr_freq_mhz
<= fixed_ddr_parm_0
[i
].max_freq
)) {
191 memcpy(&ddr_cfg_regs
,
192 fixed_ddr_parm_0
[i
].ddr_settings
,
193 sizeof(ddr_cfg_regs
));
198 if (fixed_ddr_parm_0
[i
].max_freq
== 0)
199 panic("Unsupported DDR data rate %s MT/s data rate\n",
200 strmhz(buf
, ddr_freq
));
202 ddr_size
= (phys_size_t
)2048 * 1024 * 1024;
203 fsl_ddr_set_memctl_regs(&ddr_cfg_regs
, 0, 0);
209 int fsl_initdram(void)
211 phys_size_t dram_size
;
213 #ifdef CONFIG_SYS_DDR_RAW_TIMING
214 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
215 puts("Initializing DDR....\n");
216 dram_size
= fsl_ddr_sdram();
218 dram_size
= fsl_ddr_sdram_size();
221 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
222 puts("Initialzing DDR using fixed setting\n");
223 dram_size
= fixed_sdram();
225 gd
->ram_size
= 0x80000000;
230 erratum_a008850_post();
232 #ifdef CONFIG_FSL_DEEP_SLEEP
233 fsl_dp_ddr_restore();
236 gd
->ram_size
= dram_size
;