2 * Copyright 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <fsl_ddr_sdram.h>
9 #include <fsl_ddr_dimm_params.h>
10 #ifdef CONFIG_FSL_DEEP_SLEEP
11 #include <fsl_sleep.h>
15 DECLARE_GLOBAL_DATA_PTR
;
17 void fsl_ddr_board_options(memctl_options_t
*popts
,
19 unsigned int ctrl_num
)
21 const struct board_specific_parameters
*pbsp
, *pbsp_highest
= NULL
;
25 printf("Not supported controller number %d\n", ctrl_num
);
33 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
34 * freqency and n_banks specified in board_specific_parameters table.
36 ddr_freq
= get_ddr_freq(0) / 1000000;
37 while (pbsp
->datarate_mhz_high
) {
38 if (pbsp
->n_ranks
== pdimm
->n_ranks
) {
39 if (ddr_freq
<= pbsp
->datarate_mhz_high
) {
40 popts
->clk_adjust
= pbsp
->clk_adjust
;
41 popts
->wrlvl_start
= pbsp
->wrlvl_start
;
42 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
43 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
52 printf("Error: board specific timing not found for %lu MT/s\n",
54 printf("Trying to use the highest speed (%u) parameters\n",
55 pbsp_highest
->datarate_mhz_high
);
56 popts
->clk_adjust
= pbsp_highest
->clk_adjust
;
57 popts
->wrlvl_start
= pbsp_highest
->wrlvl_start
;
58 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
59 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
61 panic("DIMM is not supported by this board");
64 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
65 pbsp
->n_ranks
, pbsp
->datarate_mhz_high
, pbsp
->rank_gb
);
67 popts
->data_bus_width
= 0; /* 64b data bus */
68 popts
->otf_burst_chop_en
= 0;
69 popts
->burst_length
= DDR_BL8
;
70 popts
->bstopre
= 0; /* enable auto precharge */
72 popts
->half_strength_driver_enable
= 0;
74 * Write leveling override
76 popts
->wrlvl_override
= 1;
77 popts
->wrlvl_sample
= 0xf;
80 * Rtt and Rtt_WR override
82 popts
->rtt_override
= 0;
84 /* Enable ZQ calibration */
87 popts
->ddr_cdr1
= DDR_CDR1_DHC_EN
| DDR_CDR1_ODT(DDR_CDR_ODT_80ohm
);
88 popts
->ddr_cdr2
= DDR_CDR2_ODT(DDR_CDR_ODT_80ohm
) |
89 DDR_CDR2_VREF_TRAIN_EN
| DDR_CDR2_VREF_RANGE_2
;
91 /* optimize cpo for erratum A-009942 */
92 popts
->cpo_sample
= 0x70;
97 phys_size_t dram_size
;
99 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
100 return fsl_ddr_sdram_size();
102 puts("Initializing DDR....using SPD\n");
104 dram_size
= fsl_ddr_sdram();
107 #ifdef CONFIG_FSL_DEEP_SLEEP
108 fsl_dp_ddr_restore();
111 erratum_a008850_post();
113 gd
->ram_size
= dram_size
;