board/freescale/ls1046aqds/ls1046aqds.c

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <fdt_support.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/fsl_serdes.h>
  13 #include <asm/arch/fdt.h>
  14 #include <asm/arch/mmu.h>
  15 #include <asm/arch/soc.h>
  16 #include <ahci.h>
  17 #include <hwconfig.h>
  18 #include <mmc.h>
  19 #include <scsi.h>
  20 #include <fm_eth.h>
  21 #include <fsl_csu.h>
  22 #include <fsl_esdhc.h>
  23 #include <fsl_ifc.h>
  24 #include <spl.h>
  25
  26 #include "../common/vid.h"
  27 #include "../common/qixis.h"
  28 #include "ls1046aqds_qixis.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 enum {
  33         MUX_TYPE_GPIO,
  34 };
  35
  36 int checkboard(void)
  37 {
  38         char buf[64];
  39 #ifndef CONFIG_SD_BOOT
  40         u8 sw;
  41 #endif
  42
  43         puts("Board: LS1046AQDS, boot from ");
  44
  45 #ifdef CONFIG_SD_BOOT
  46         puts("SD\n");
  47 #else
  48         sw = QIXIS_READ(brdcfg[0]);
  49         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  50
  51         if (sw < 0x8)
  52                 printf("vBank: %d\n", sw);
  53         else if (sw == 0x8)
  54                 puts("PromJet\n");
  55         else if (sw == 0x9)
  56                 puts("NAND\n");
  57         else if (sw == 0xF)
  58                 printf("QSPI\n");
  59         else
  60                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  61 #endif
  62
  63         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
  64                QIXIS_READ(id), QIXIS_READ(arch));
  65
  66         printf("FPGA:  v%d (%s), build %d\n",
  67                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  68                (int)qixis_read_minor());
  69
  70         return 0;
  71 }
  72
  73 bool if_board_diff_clk(void)
  74 {
  75         u8 diff_conf = QIXIS_READ(brdcfg[11]);
  76
  77         return diff_conf & 0x40;
  78 }
  79
  80 unsigned long get_board_sys_clk(void)
  81 {
  82         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  83
  84         switch (sysclk_conf & 0x0f) {
  85         case QIXIS_SYSCLK_64:
  86                 return 64000000;
  87         case QIXIS_SYSCLK_83:
  88                 return 83333333;
  89         case QIXIS_SYSCLK_100:
  90                 return 100000000;
  91         case QIXIS_SYSCLK_125:
  92                 return 125000000;
  93         case QIXIS_SYSCLK_133:
  94                 return 133333333;
  95         case QIXIS_SYSCLK_150:
  96                 return 150000000;
  97         case QIXIS_SYSCLK_160:
  98                 return 160000000;
  99         case QIXIS_SYSCLK_166:
 100                 return 166666666;
 101         }
 102
 103         return 66666666;
 104 }
 105
 106 unsigned long get_board_ddr_clk(void)
 107 {
 108         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 109
 110         if (if_board_diff_clk())
 111                 return get_board_sys_clk();
 112         switch ((ddrclk_conf & 0x30) >> 4) {
 113         case QIXIS_DDRCLK_100:
 114                 return 100000000;
 115         case QIXIS_DDRCLK_125:
 116                 return 125000000;
 117         case QIXIS_DDRCLK_133:
 118                 return 133333333;
 119         }
 120
 121         return 66666666;
 122 }
 123
 124 #ifdef CONFIG_LPUART
 125 u32 get_lpuart_clk(void)
 126 {
 127         return gd->bus_clk;
 128 }
 129 #endif
 130
 131 int select_i2c_ch_pca9547(u8 ch)
 132 {
 133         int ret;
 134
 135         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 136         if (ret) {
 137                 puts("PCA: failed to select proper channel\n");
 138                 return ret;
 139         }
 140
 141         return 0;
 142 }
 143
 144 int dram_init(void)
 145 {
 146         /*
 147          * When resuming from deep sleep, the I2C channel may not be
 148          * in the default channel. So, switch to the default channel
 149          * before accessing DDR SPD.
 150          */
 151         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 152         gd->ram_size = initdram(0);
 153 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 154         /* This will break-before-make MMU for DDR */
 155         update_early_mmu_table();
 156 #endif
 157
 158         return 0;
 159 }
 160
 161 int i2c_multiplexer_select_vid_channel(u8 channel)
 162 {
 163         return select_i2c_ch_pca9547(channel);
 164 }
 165
 166 int board_early_init_f(void)
 167 {
 168 #ifdef CONFIG_HAS_FSL_XHCI_USB
 169         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 170         u32 usb_pwrfault;
 171 #endif
 172 #ifdef CONFIG_LPUART
 173         u8 uart;
 174 #endif
 175
 176 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 177         i2c_early_init_f();
 178 #endif
 179         fsl_lsch2_early_init_f();
 180
 181 #ifdef CONFIG_HAS_FSL_XHCI_USB
 182         out_be32(&scfg->rcwpmuxcr0, 0x3333);
 183         out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 184         usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
 185                         SCFG_USBPWRFAULT_USB3_SHIFT) |
 186                         (SCFG_USBPWRFAULT_DEDICATED <<
 187                         SCFG_USBPWRFAULT_USB2_SHIFT) |
 188                         (SCFG_USBPWRFAULT_SHARED <<
 189                         SCFG_USBPWRFAULT_USB1_SHIFT);
 190         out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 191 #endif
 192
 193 #ifdef CONFIG_LPUART
 194         /* We use lpuart0 as system console */
 195         uart = QIXIS_READ(brdcfg[14]);
 196         uart &= ~CFG_UART_MUX_MASK;
 197         uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 198         QIXIS_WRITE(brdcfg[14], uart);
 199 #endif
 200
 201         return 0;
 202 }
 203
 204 #ifdef CONFIG_FSL_DEEP_SLEEP
 205 /* determine if it is a warm boot */
 206 bool is_warm_boot(void)
 207 {
 208 #define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 209         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 210
 211         if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 212                 return 1;
 213
 214         return 0;
 215 }
 216 #endif
 217
 218 int config_board_mux(int ctrl_type)
 219 {
 220         u8 reg14;
 221
 222         reg14 = QIXIS_READ(brdcfg[14]);
 223
 224         switch (ctrl_type) {
 225         case MUX_TYPE_GPIO:
 226                 reg14 = (reg14 & (~0x6)) | 0x2;
 227                 break;
 228         default:
 229                 puts("Unsupported mux interface type\n");
 230                 return -1;
 231         }
 232
 233         QIXIS_WRITE(brdcfg[14], reg14);
 234
 235         return 0;
 236 }
 237
 238 int config_serdes_mux(void)
 239 {
 240         return 0;
 241 }
 242
 243 #ifdef CONFIG_MISC_INIT_R
 244 int misc_init_r(void)
 245 {
 246         if (hwconfig("gpio"))
 247                 config_board_mux(MUX_TYPE_GPIO);
 248
 249         return 0;
 250 }
 251 #endif
 252
 253 int board_init(void)
 254 {
 255         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 256
 257 #ifdef CONFIG_SYS_FSL_SERDES
 258         config_serdes_mux();
 259 #endif
 260
 261 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 262         enable_layerscape_ns_access();
 263 #endif
 264
 265         if (adjust_vdd(0))
 266                 printf("Warning: Adjusting core voltage failed.\n");
 267
 268         return 0;
 269 }
 270
 271 #ifdef CONFIG_OF_BOARD_SETUP
 272 int ft_board_setup(void *blob, bd_t *bd)
 273 {
 274         u64 base[CONFIG_NR_DRAM_BANKS];
 275         u64 size[CONFIG_NR_DRAM_BANKS];
 276         u8 reg;
 277
 278         /* fixup DT for the two DDR banks */
 279         base[0] = gd->bd->bi_dram[0].start;
 280         size[0] = gd->bd->bi_dram[0].size;
 281         base[1] = gd->bd->bi_dram[1].start;
 282         size[1] = gd->bd->bi_dram[1].size;
 283
 284         fdt_fixup_memory_banks(blob, base, size, 2);
 285         ft_cpu_setup(blob, bd);
 286
 287 #ifdef CONFIG_SYS_DPAA_FMAN
 288         fdt_fixup_fman_ethernet(blob);
 289         fdt_fixup_board_enet(blob);
 290 #endif
 291
 292         reg = QIXIS_READ(brdcfg[0]);
 293         reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 294
 295         /* Disable IFC if QSPI is enabled */
 296         if (reg == 0xF)
 297                 do_fixup_by_compat(blob, "fsl,ifc",
 298                                    "status", "disabled", 8 + 1, 1);
 299
 300         return 0;
 301 }
 302 #endif
 303
 304 u8 flash_read8(void *addr)
 305 {
 306         return __raw_readb(addr + 1);
 307 }
 308
 309 void flash_write16(u16 val, void *addr)
 310 {
 311         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 312
 313         __raw_writew(shftval, addr);
 314 }
 315
 316 u16 flash_read16(void *addr)
 317 {
 318         u16 val = __raw_readw(addr);
 319
 320         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 321 }