board/freescale/ls2080aqds/ddr.h

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __DDR_H__
   8 #define __DDR_H__
   9 struct board_specific_parameters {
  10         u32 n_ranks;
  11         u32 datarate_mhz_high;
  12         u32 rank_gb;
  13         u32 clk_adjust;
  14         u32 wrlvl_start;
  15         u32 wrlvl_ctl_2;
  16         u32 wrlvl_ctl_3;
  17 };
  18
  19 /*
  20  * These tables contain all valid speeds we want to override with board
  21  * specific parameters. datarate_mhz_high values need to be in ascending order
  22  * for each n_ranks group.
  23  */
  24
  25 static const struct board_specific_parameters udimm0[] = {
  26         /*
  27          * memory controller 0
  28          *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
  29          * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
  30          */
  31         {2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
  32         {2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
  33         {2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
  34         {2,  2300, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
  35         {}
  36 };
  37
  38 /* DP-DDR DIMM */
  39 static const struct board_specific_parameters udimm2[] = {
  40         /*
  41          * memory controller 2
  42          *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
  43          * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
  44          */
  45         {2,  1350, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
  46         {2,  1666, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
  47         {2,  1900, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
  48         {2,  2200, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
  49         {}
  50 };
  51
  52 static const struct board_specific_parameters rdimm0[] = {
  53         /*
  54          * memory controller 0
  55          *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
  56          * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
  57          */
  58         {2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
  59         {2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
  60         {2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
  61         {2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
  62         {}
  63 };
  64
  65 /* DP-DDR DIMM */
  66 static const struct board_specific_parameters rdimm2[] = {
  67         /*
  68          * memory controller 2
  69          *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
  70          * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
  71          */
  72         {2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
  73         {2,  1666, 0, 4,     7, 0x0B0A090C, 0x0D0F100B,},
  74         {2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
  75         {2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
  76         {}
  77 };
  78
  79 static const struct board_specific_parameters *udimms[] = {
  80         udimm0,
  81         udimm0,
  82         udimm2,
  83 };
  84
  85 static const struct board_specific_parameters *rdimms[] = {
  86         rdimm0,
  87         rdimm0,
  88         rdimm2,
  89 };
  90
  91
  92 #endif