board/freescale/ls2085aqds/ls2085aqds.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <malloc.h>
   8 #include <errno.h>
   9 #include <netdev.h>
  10 #include <fsl_ifc.h>
  11 #include <fsl_ddr.h>
  12 #include <asm/io.h>
  13 #include <fdt_support.h>
  14 #include <libfdt.h>
  15 #include <fsl_debug_server.h>
  16 #include <fsl-mc/fsl_mc.h>
  17 #include <environment.h>
  18 #include <i2c.h>
  19 #include <asm/arch-fsl-lsch3/soc.h>
  20
  21 #include "../common/qixis.h"
  22 #include "ls2085aqds_qixis.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 unsigned long long get_qixis_addr(void)
  27 {
  28         unsigned long long addr;
  29
  30         if (gd->flags & GD_FLG_RELOC)
  31                 addr = QIXIS_BASE_PHYS;
  32         else
  33                 addr = QIXIS_BASE_PHYS_EARLY;
  34
  35         /*
  36          * IFC address under 256MB is mapped to 0x30000000, any address above
  37          * is mapped to 0x5_10000000 up to 4GB.
  38          */
  39         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  40
  41         return addr;
  42 }
  43
  44 int checkboard(void)
  45 {
  46         char buf[64];
  47         u8 sw;
  48         static const char *const freq[] = {"100", "125", "156.25",
  49                                             "100 separate SSCG"};
  50         int clock;
  51
  52         sw = QIXIS_READ(arch);
  53         printf("Board: %s, ", CONFIG_IDENT_STRING);
  54         printf("Board Arch: V%d, ", sw >> 4);
  55         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  56
  57         sw = QIXIS_READ(brdcfg[0]);
  58         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  59
  60         if (sw < 0x8)
  61                 printf("vBank: %d\n", sw);
  62         else if (sw == 0x8)
  63                 puts("PromJet\n");
  64         else if (sw == 0x9)
  65                 puts("NAND\n");
  66         else if (sw == 0x15)
  67                 printf("IFCCard\n");
  68         else
  69                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  70
  71         printf("FPGA: v%d (%s), build %d",
  72                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  73                (int)qixis_read_minor());
  74         /* the timestamp string contains "\n" at the end */
  75         printf(" on %s", qixis_read_time(buf));
  76
  77         /*
  78          * Display the actual SERDES reference clocks as configured by the
  79          * dip switches on the board.  Note that the SWx registers could
  80          * technically be set to force the reference clocks to match the
  81          * values that the SERDES expects (or vice versa).  For now, however,
  82          * we just display both values and hope the user notices when they
  83          * don't match.
  84          */
  85         puts("SERDES1 Reference : ");
  86         sw = QIXIS_READ(brdcfg[2]);
  87         clock = (sw >> 6) & 3;
  88         printf("Clock1 = %sMHz ", freq[clock]);
  89         clock = (sw >> 4) & 3;
  90         printf("Clock2 = %sMHz", freq[clock]);
  91
  92         puts("\nSERDES2 Reference : ");
  93         clock = (sw >> 2) & 3;
  94         printf("Clock1 = %sMHz ", freq[clock]);
  95         clock = (sw >> 0) & 3;
  96         printf("Clock2 = %sMHz\n", freq[clock]);
  97
  98         return 0;
  99 }
 100
 101 unsigned long get_board_sys_clk(void)
 102 {
 103         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 104
 105         switch (sysclk_conf & 0x0F) {
 106         case QIXIS_SYSCLK_83:
 107                 return 83333333;
 108         case QIXIS_SYSCLK_100:
 109                 return 100000000;
 110         case QIXIS_SYSCLK_125:
 111                 return 125000000;
 112         case QIXIS_SYSCLK_133:
 113                 return 133333333;
 114         case QIXIS_SYSCLK_150:
 115                 return 150000000;
 116         case QIXIS_SYSCLK_160:
 117                 return 160000000;
 118         case QIXIS_SYSCLK_166:
 119                 return 166666666;
 120         }
 121         return 66666666;
 122 }
 123
 124 unsigned long get_board_ddr_clk(void)
 125 {
 126         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 127
 128         switch ((ddrclk_conf & 0x30) >> 4) {
 129         case QIXIS_DDRCLK_100:
 130                 return 100000000;
 131         case QIXIS_DDRCLK_125:
 132                 return 125000000;
 133         case QIXIS_DDRCLK_133:
 134                 return 133333333;
 135         }
 136         return 66666666;
 137 }
 138
 139 int select_i2c_ch_pca9547(u8 ch)
 140 {
 141         int ret;
 142
 143         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 144         if (ret) {
 145                 puts("PCA: failed to select proper channel\n");
 146                 return ret;
 147         }
 148
 149         return 0;
 150 }
 151
 152 int board_init(void)
 153 {
 154         init_final_memctl_regs();
 155
 156 #ifdef CONFIG_ENV_IS_NOWHERE
 157         gd->env_addr = (ulong)&default_environment[0];
 158 #endif
 159         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 160
 161         return 0;
 162 }
 163
 164 int board_early_init_f(void)
 165 {
 166         fsl_lsch3_early_init_f();
 167         return 0;
 168 }
 169
 170 void detail_board_ddr_info(void)
 171 {
 172         puts("\nDDR    ");
 173         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 174         print_ddr_info(0);
 175         if (gd->bd->bi_dram[2].size) {
 176                 puts("\nDP-DDR ");
 177                 print_size(gd->bd->bi_dram[2].size, "");
 178                 print_ddr_info(CONFIG_DP_DDR_CTRL);
 179         }
 180 }
 181
 182 int dram_init(void)
 183 {
 184         gd->ram_size = initdram(0);
 185
 186         return 0;
 187 }
 188
 189 #if defined(CONFIG_ARCH_MISC_INIT)
 190 int arch_misc_init(void)
 191 {
 192 #ifdef CONFIG_FSL_DEBUG_SERVER
 193         debug_server_init();
 194 #endif
 195
 196         return 0;
 197 }
 198 #endif
 199
 200 unsigned long get_dram_size_to_hide(void)
 201 {
 202         unsigned long dram_to_hide = 0;
 203
 204 /* Carve the Debug Server private DRAM block from the end of DRAM */
 205 #ifdef CONFIG_FSL_DEBUG_SERVER
 206         dram_to_hide += debug_server_get_dram_block_size();
 207 #endif
 208
 209 /* Carve the MC private DRAM block from the end of DRAM */
 210 #ifdef CONFIG_FSL_MC_ENET
 211         dram_to_hide += mc_get_dram_block_size();
 212 #endif
 213
 214         return dram_to_hide;
 215 }
 216
 217 #ifdef CONFIG_FSL_MC_ENET
 218 void fdt_fixup_board_enet(void *fdt)
 219 {
 220         int offset;
 221
 222         offset = fdt_path_offset(fdt, "/fsl-mc");
 223
 224         if (offset < 0)
 225                 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
 226
 227         if (offset < 0) {
 228                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 229                        __func__, offset);
 230                 return;
 231         }
 232
 233         if (get_mc_boot_status() == 0)
 234                 fdt_status_okay(fdt, offset);
 235         else
 236                 fdt_status_fail(fdt, offset);
 237 }
 238 #endif
 239
 240 #ifdef CONFIG_OF_BOARD_SETUP
 241 int ft_board_setup(void *blob, bd_t *bd)
 242 {
 243         phys_addr_t base;
 244         phys_size_t size;
 245
 246         ft_cpu_setup(blob, bd);
 247
 248         /* limit the memory size to bank 1 until Linux can handle 40-bit PA */
 249         base = getenv_bootm_low();
 250         size = getenv_bootm_size();
 251         fdt_fixup_memory(blob, (u64)base, (u64)size);
 252
 253 #ifdef CONFIG_FSL_MC_ENET
 254         fdt_fixup_board_enet(blob);
 255         fsl_mc_ldpaa_exit(bd);
 256 #endif
 257
 258         return 0;
 259 }
 260 #endif
 261
 262 void qixis_dump_switch(void)
 263 {
 264         int i, nr_of_cfgsw;
 265
 266         QIXIS_WRITE(cms[0], 0x00);
 267         nr_of_cfgsw = QIXIS_READ(cms[1]);
 268
 269         puts("DIP switch settings dump:\n");
 270         for (i = 1; i <= nr_of_cfgsw; i++) {
 271                 QIXIS_WRITE(cms[0], i);
 272                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 273         }
 274 }