board/freescale/ls2085ardb/ls2085ardb.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <malloc.h>
   8 #include <errno.h>
   9 #include <netdev.h>
  10 #include <fsl_ifc.h>
  11 #include <fsl_ddr.h>
  12 #include <asm/io.h>
  13 #include <hwconfig.h>
  14 #include <fdt_support.h>
  15 #include <libfdt.h>
  16 #include <fsl_debug_server.h>
  17 #include <fsl-mc/fsl_mc.h>
  18 #include <environment.h>
  19 #include <i2c.h>
  20 #include <asm/arch-fsl-lsch3/soc.h>
  21
  22 #include "../common/qixis.h"
  23 #include "ls2085ardb_qixis.h"
  24
  25 #define PIN_MUX_SEL_SDHC        0x00
  26
  27 #define SET_SDHC_MUX_SEL(reg, value)    ((reg & 0xf0) | value)
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 enum {
  31         MUX_TYPE_SDHC,
  32 };
  33
  34 unsigned long long get_qixis_addr(void)
  35 {
  36         unsigned long long addr;
  37
  38         if (gd->flags & GD_FLG_RELOC)
  39                 addr = QIXIS_BASE_PHYS;
  40         else
  41                 addr = QIXIS_BASE_PHYS_EARLY;
  42
  43         /*
  44          * IFC address under 256MB is mapped to 0x30000000, any address above
  45          * is mapped to 0x5_10000000 up to 4GB.
  46          */
  47         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  48
  49         return addr;
  50 }
  51
  52 int checkboard(void)
  53 {
  54         u8 sw;
  55         char buf[15];
  56
  57         cpu_name(buf);
  58         printf("Board: %s-RDB, ", buf);
  59
  60         sw = QIXIS_READ(arch);
  61         printf("Board Arch: V%d, ", sw >> 4);
  62         printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
  63
  64         sw = QIXIS_READ(brdcfg[0]);
  65         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  66
  67         if (sw < 0x8)
  68                 printf("vBank: %d\n", sw);
  69         else if (sw == 0x9)
  70                 puts("NAND\n");
  71         else
  72                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  73
  74         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  75
  76         puts("SERDES1 Reference : ");
  77         printf("Clock1 = 156.25MHz ");
  78         printf("Clock2 = 156.25MHz");
  79
  80         puts("\nSERDES2 Reference : ");
  81         printf("Clock1 = 100MHz ");
  82         printf("Clock2 = 100MHz\n");
  83
  84         return 0;
  85 }
  86
  87 unsigned long get_board_sys_clk(void)
  88 {
  89         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  90
  91         switch (sysclk_conf & 0x0F) {
  92         case QIXIS_SYSCLK_83:
  93                 return 83333333;
  94         case QIXIS_SYSCLK_100:
  95                 return 100000000;
  96         case QIXIS_SYSCLK_125:
  97                 return 125000000;
  98         case QIXIS_SYSCLK_133:
  99                 return 133333333;
 100         case QIXIS_SYSCLK_150:
 101                 return 150000000;
 102         case QIXIS_SYSCLK_160:
 103                 return 160000000;
 104         case QIXIS_SYSCLK_166:
 105                 return 166666666;
 106         }
 107         return 66666666;
 108 }
 109
 110 int select_i2c_ch_pca9547(u8 ch)
 111 {
 112         int ret;
 113
 114         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 115         if (ret) {
 116                 puts("PCA: failed to select proper channel\n");
 117                 return ret;
 118         }
 119
 120         return 0;
 121 }
 122
 123 int board_init(void)
 124 {
 125         init_final_memctl_regs();
 126
 127 #ifdef CONFIG_ENV_IS_NOWHERE
 128         gd->env_addr = (ulong)&default_environment[0];
 129 #endif
 130         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 131
 132         QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 133
 134         return 0;
 135 }
 136
 137 int board_early_init_f(void)
 138 {
 139         fsl_lsch3_early_init_f();
 140         return 0;
 141 }
 142
 143 int config_board_mux(int ctrl_type)
 144 {
 145         u8 reg5;
 146
 147         reg5 = QIXIS_READ(brdcfg[5]);
 148
 149         switch (ctrl_type) {
 150         case MUX_TYPE_SDHC:
 151                 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
 152                 break;
 153         default:
 154                 printf("Wrong mux interface type\n");
 155                 return -1;
 156         }
 157
 158         QIXIS_WRITE(brdcfg[5], reg5);
 159
 160         return 0;
 161 }
 162
 163 int misc_init_r(void)
 164 {
 165         if (hwconfig("sdhc"))
 166                 config_board_mux(MUX_TYPE_SDHC);
 167
 168         return 0;
 169 }
 170
 171 void detail_board_ddr_info(void)
 172 {
 173         puts("\nDDR    ");
 174         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 175         print_ddr_info(0);
 176         if (gd->bd->bi_dram[2].size) {
 177                 puts("\nDP-DDR ");
 178                 print_size(gd->bd->bi_dram[2].size, "");
 179                 print_ddr_info(CONFIG_DP_DDR_CTRL);
 180         }
 181 }
 182
 183 int dram_init(void)
 184 {
 185         gd->ram_size = initdram(0);
 186
 187         return 0;
 188 }
 189
 190 #if defined(CONFIG_ARCH_MISC_INIT)
 191 int arch_misc_init(void)
 192 {
 193 #ifdef CONFIG_FSL_DEBUG_SERVER
 194         debug_server_init();
 195 #endif
 196
 197         return 0;
 198 }
 199 #endif
 200
 201 unsigned long get_dram_size_to_hide(void)
 202 {
 203         unsigned long dram_to_hide = 0;
 204
 205 /* Carve the Debug Server private DRAM block from the end of DRAM */
 206 #ifdef CONFIG_FSL_DEBUG_SERVER
 207         dram_to_hide += debug_server_get_dram_block_size();
 208 #endif
 209
 210 /* Carve the MC private DRAM block from the end of DRAM */
 211 #ifdef CONFIG_FSL_MC_ENET
 212         dram_to_hide += mc_get_dram_block_size();
 213 #endif
 214
 215         return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
 216 }
 217
 218 #ifdef CONFIG_FSL_MC_ENET
 219 void fdt_fixup_board_enet(void *fdt)
 220 {
 221         int offset;
 222
 223         offset = fdt_path_offset(fdt, "/fsl-mc");
 224
 225         if (offset < 0)
 226                 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
 227
 228         if (offset < 0) {
 229                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 230                        __func__, offset);
 231                 return;
 232         }
 233
 234         if (get_mc_boot_status() == 0)
 235                 fdt_status_okay(fdt, offset);
 236         else
 237                 fdt_status_fail(fdt, offset);
 238 }
 239 #endif
 240
 241 #ifdef CONFIG_OF_BOARD_SETUP
 242 int ft_board_setup(void *blob, bd_t *bd)
 243 {
 244         u64 base[CONFIG_NR_DRAM_BANKS];
 245         u64 size[CONFIG_NR_DRAM_BANKS];
 246
 247         ft_cpu_setup(blob, bd);
 248
 249         /* fixup DT for the two GPP DDR banks */
 250         base[0] = gd->bd->bi_dram[0].start;
 251         size[0] = gd->bd->bi_dram[0].size;
 252         base[1] = gd->bd->bi_dram[1].start;
 253         size[1] = gd->bd->bi_dram[1].size;
 254
 255         fdt_fixup_memory_banks(blob, base, size, 2);
 256
 257 #ifdef CONFIG_FSL_MC_ENET
 258         fdt_fixup_board_enet(blob);
 259         fsl_mc_ldpaa_exit(bd);
 260 #endif
 261
 262         return 0;
 263 }
 264 #endif
 265
 266 void qixis_dump_switch(void)
 267 {
 268         int i, nr_of_cfgsw;
 269
 270         QIXIS_WRITE(cms[0], 0x00);
 271         nr_of_cfgsw = QIXIS_READ(cms[1]);
 272
 273         puts("DIP switch settings dump:\n");
 274         for (i = 1; i <= nr_of_cfgsw; i++) {
 275                 QIXIS_WRITE(cms[0], i);
 276                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 277         }
 278 }
 279
 280 /*
 281  * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
 282  * Both slots has 0x54, resulting 2nd slot unusable.
 283  */
 284 void update_spd_address(unsigned int ctrl_num,
 285                         unsigned int slot,
 286                         unsigned int *addr)
 287 {
 288         u8 sw;
 289
 290         sw = QIXIS_READ(arch);
 291         if ((sw & 0xf) < 0x3) {
 292                 if (ctrl_num == 1 && slot == 0)
 293                         *addr = SPD_EEPROM_ADDRESS4;
 294                 else if (ctrl_num == 1 && slot == 1)
 295                         *addr = SPD_EEPROM_ADDRESS3;
 296         }
 297 }