board/freescale/m5235evb/m5235evb.c

   1 /*
   2  * (C) Copyright 2000-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <config.h>
  12 #include <common.h>
  13 #include <asm/immap.h>
  14 #include <asm/io.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 int checkboard(void)
  19 {
  20         puts("Board: ");
  21         puts("Freescale M5235 EVB\n");
  22         return 0;
  23 };
  24
  25 phys_size_t initdram(int board_type)
  26 {
  27         sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
  28         gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
  29         u32 dramsize, i, dramclk;
  30
  31         /*
  32          * When booting from external Flash, the port-size is less than
  33          * the port-size of SDRAM.  In this case it is necessary to enable
  34          * Data[15:0] on Port Address/Data.
  35          */
  36         out_8(&gpio->par_ad,
  37                 GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
  38                 GPIO_PAR_AD_DATAL);
  39
  40         /* Initialize PAR to enable SDRAM signals */
  41         out_8(&gpio->par_sdram,
  42                 GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS |
  43                 GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
  44                 GPIO_PAR_SDRAM_SDCS(3));
  45
  46         dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
  47         for (i = 0x13; i < 0x20; i++) {
  48                 if (dramsize == (1 << i))
  49                         break;
  50         }
  51         i--;
  52
  53         if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) {
  54                 dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
  55
  56                 /* Initialize DRAM Control Register: DCR */
  57                 out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS |
  58                         SDRAMC_DCR_RTIM_6CLKS |
  59                         SDRAMC_DCR_RC((15 * dramclk) >> 4));
  60
  61                 /* Initialize DACR0 */
  62                 out_be32(&sdram->dacr0,
  63                         SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
  64                         SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
  65                         SDRAMC_DARCn_PS_32);
  66                 asm("nop");
  67
  68                 /* Initialize DMR0 */
  69                 out_be32(&sdram->dmr0,
  70                         ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V);
  71                 asm("nop");
  72
  73                 /* Set IP (bit 3) in DACR */
  74                 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP);
  75
  76                 /* Wait 30ns to allow banks to precharge */
  77                 for (i = 0; i < 5; i++) {
  78                         asm("nop");
  79                 }
  80
  81                 /* Write to this block to initiate precharge */
  82                 *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
  83
  84                 /*  Set RE (bit 15) in DACR */
  85                 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
  86
  87                 /* Wait for at least 8 auto refresh cycles to occur */
  88                 for (i = 0; i < 0x2000; i++) {
  89                         asm("nop");
  90                 }
  91
  92                 /* Finish the configuration by issuing the MRS. */
  93                 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS);
  94                 asm("nop");
  95
  96                 /* Write to the SDRAM Mode Register */
  97                 *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
  98         }
  99
 100         return dramsize;
 101 };
 102
 103 int testdram(void)
 104 {
 105         /* TODO: XXX XXX XXX */
 106         printf("DRAM test not implemented!\n");
 107
 108         return (0);
 109 }