board/freescale/m5249evb/m5249evb.c

   1 /*
   2  * (C) Copyright 2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <malloc.h>
  11 #include <asm/immap.h>
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 int checkboard (void) {
  16         ulong val;
  17         uchar val8;
  18
  19         puts ("Board: ");
  20         puts("Freescale M5249EVB");
  21         val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
  22         printf(" (Switch=%1X)\n", val8);
  23
  24         /*
  25          * Set LED on
  26          */
  27         val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
  28         mbar2_writeLong(MCFSIM_GPIO1_OUT, val);   /* Set LED on */
  29
  30         return 0;
  31 };
  32
  33
  34 int initdram(void)
  35 {
  36         unsigned long   junk = 0xa5a59696;
  37
  38         /*
  39          *  Note:
  40          *      RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
  41          */
  42
  43 #ifdef CONFIG_SYS_FAST_CLK
  44         /*
  45          * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
  46          * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
  47          */
  48         mbar_writeShort(MCFSIM_DCR, 0x8239);
  49 #elif CONFIG_SYS_PLL_BYPASS
  50         /*
  51          * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
  52          * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
  53          */
  54         mbar_writeShort(MCFSIM_DCR, 0x8202);
  55 #else
  56         /*
  57          * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
  58          * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
  59          */
  60         mbar_writeShort(MCFSIM_DCR, 0x8222);
  61 #endif
  62
  63         /*
  64          * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
  65          * PM=1 (continuous page mode)
  66          */
  67
  68         /* RE=0 (keep auto-refresh disabled while setting up registers) */
  69         mbar_writeLong(MCFSIM_DACR0, 0x00003324);
  70
  71         /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
  72         mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
  73
  74         /** Precharge sequence **/
  75         mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
  76         *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
  77         udelay(0x10); /* Allow several Precharge cycles */
  78
  79         /** Refresh Sequence **/
  80         mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
  81         udelay(0x7d0); /* Allow gobs of refresh cycles */
  82
  83         /** Mode Register initialization **/
  84         mbar_writeLong(MCFSIM_DACR0, 0x0000b364);  /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
  85         *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
  86
  87         gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  88
  89         return 0;
  90 };
  91
  92
  93 int testdram (void) {
  94         /* TODO: XXX XXX XXX */
  95         printf ("DRAM test not implemented!\n");
  96
  97         return (0);
  98 }