board/freescale/m5253demo/m5253demo.c

   1 /*
   2  * (C) Copyright 2000-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
   6  * Hayden Fraser (Hayden.Fraser@freescale.com)
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/immap.h>
  13 #include <netdev.h>
  14 #include <asm/io.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 int checkboard(void)
  19 {
  20         puts("Board: ");
  21         puts("Freescale MCF5253 DEMO\n");
  22         return 0;
  23 };
  24
  25 int dram_init(void)
  26 {
  27         u32 dramsize = 0;
  28
  29         /*
  30          * Check to see if the SDRAM has already been initialized
  31          * by a run control tool
  32          */
  33         if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
  34                 u32 RC, temp;
  35
  36                 RC = (CONFIG_SYS_CLK / 1000000) >> 1;
  37                 RC = (RC * 15) >> 4;
  38
  39                 /* Initialize DRAM Control Register: DCR */
  40                 mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
  41                 __asm__("nop");
  42
  43                 mbar_writeLong(MCFSIM_DACR0, 0x00003224);
  44                 __asm__("nop");
  45
  46                 /* Initialize DMR0 */
  47                 dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
  48                 temp = (dramsize - 1) & 0xFFFC0000;
  49                 mbar_writeLong(MCFSIM_DMR0, temp | 1);
  50                 __asm__("nop");
  51
  52                 mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
  53                 mb();
  54                 __asm__("nop");
  55
  56                 /* Write to this block to initiate precharge */
  57                 *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
  58                 mb();
  59                 __asm__("nop");
  60
  61                 /* Set RE bit in DACR */
  62                 mbar_writeLong(MCFSIM_DACR0,
  63                                mbar_readLong(MCFSIM_DACR0) | 0x8000);
  64                 __asm__("nop");
  65
  66                 /* Wait for at least 8 auto refresh cycles to occur */
  67                 udelay(500);
  68
  69                 /* Finish the configuration by issuing the MRS */
  70                 mbar_writeLong(MCFSIM_DACR0,
  71                                mbar_readLong(MCFSIM_DACR0) | 0x0040);
  72                 __asm__("nop");
  73
  74                 *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
  75                 mb();
  76         }
  77
  78         gd->ram_size = dramsize;
  79
  80         return 0;
  81 }
  82
  83 int testdram(void)
  84 {
  85         /* TODO: XXX XXX XXX */
  86         printf("DRAM test not implemented!\n");
  87
  88         return (0);
  89 }
  90
  91 #ifdef CONFIG_IDE
  92 #include <ata.h>
  93 int ide_preinit(void)
  94 {
  95         return (0);
  96 }
  97
  98 void ide_set_reset(int idereset)
  99 {
 100         atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
 101         long period;
 102         /*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
 103         int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},       /* PIO 0 */
 104         {50, 125, 45, 20, 35, 5, 15, 0, 35},    /* PIO 1 */
 105         {30, 100, 30, 15, 20, 5, 10, 0, 35},    /* PIO 2 */
 106         {30, 80, 30, 10, 20, 5, 10, 0, 35},     /* PIO 3 */
 107         {25, 70, 20, 10, 20, 5, 10, 0, 35}      /* PIO 4 */
 108         };
 109
 110         if (idereset) {
 111                 /* control reset */
 112                 out_8(&ata->cr, 0);
 113                 udelay(100);
 114         } else {
 115                 mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
 116
 117 #define CALC_TIMING(t) (t + period - 1) / period
 118                 period = 1000000000 / (CONFIG_SYS_CLK / 2);     /* period in ns */
 119
 120                 /*ata->ton = CALC_TIMING (180); */
 121                 out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
 122                 out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
 123                 out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
 124                 out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
 125                 out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
 126                 out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
 127                 out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
 128
 129                 /* IORDY enable */
 130                 out_8(&ata->cr, 0x40);
 131                 udelay(2000);
 132                 /* IORDY enable */
 133                 setbits_8(&ata->cr, 0x01);
 134         }
 135 }
 136 #endif                          /* CONFIG_IDE */
 137
 138
 139 #ifdef CONFIG_DRIVER_DM9000
 140 int board_eth_init(bd_t *bis)
 141 {
 142         return dm9000_initialize(bis);
 143 }
 144 #endif