board/freescale/mpc5121ads/mpc5121ads.c

   1 /*
   2  * (C) Copyright 2007-2009 DENX Software Engineering
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <common.h>
  25 #include <asm/bitops.h>
  26 #include <command.h>
  27 #include <asm/io.h>
  28 #include <asm/processor.h>
  29 #include <asm/mpc512x.h>
  30 #include <fdt_support.h>
  31 #ifdef CONFIG_MISC_INIT_R
  32 #include <i2c.h>
  33 #endif
  34 #include <net.h>
  35
  36 #include <linux/mtd/mtd.h>
  37 #include <linux/mtd/nand.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 /* Clocks in use */
  42 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
  43                          CLOCK_SCCR1_DDR_EN |                           \
  44                          CLOCK_SCCR1_FEC_EN |                           \
  45                          CLOCK_SCCR1_LPC_EN |                           \
  46                          CLOCK_SCCR1_NFC_EN |                           \
  47                          CLOCK_SCCR1_PATA_EN |                          \
  48                          CLOCK_SCCR1_PCI_EN |                           \
  49                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
  50                          CLOCK_SCCR1_PSCFIFO_EN |                       \
  51                          CLOCK_SCCR1_TPR_EN)
  52
  53 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN |           \
  54                          CLOCK_SCCR2_I2C_EN |           \
  55                          CLOCK_SCCR2_MEM_EN |           \
  56                          CLOCK_SCCR2_SPDIF_EN |         \
  57                          CLOCK_SCCR2_USB1_EN |          \
  58                          CLOCK_SCCR2_USB2_EN)
  59
  60 void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
  61
  62 /* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
  63 extern int mpc5121_nfc_chip;
  64
  65 /* Control chips select signal on MPC5121ADS board */
  66 void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
  67 {
  68         unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
  69         u8 v;
  70
  71         v = in_8(csreg);
  72         v |= 0x0F;
  73
  74         if (chip >= 0) {
  75                 __mpc5121_nfc_select_chip(mtd, 0);
  76                 v &= ~(1 << mpc5121_nfc_chip);
  77         } else {
  78                 __mpc5121_nfc_select_chip(mtd, -1);
  79         }
  80
  81         out_8(csreg, v);
  82 }
  83
  84 int board_early_init_f(void)
  85 {
  86         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  87
  88         /*
  89          * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
  90          *
  91          * Without this the flash identification routine fails, as it needs to issue
  92          * write commands in order to establish the device ID.
  93          */
  94
  95 #ifdef CONFIG_MPC5121ADS_REV2
  96         out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
  97 #else
  98         if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
  99                 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
 100         } else {
 101                 /* running from Backup flash */
 102                 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
 103         }
 104 #endif
 105
 106         /*
 107          * Enable clocks
 108          */
 109         out_be32 (&im->clk.sccr[0], SCCR1_CLOCKS_EN);
 110         out_be32 (&im->clk.sccr[1], SCCR2_CLOCKS_EN);
 111 #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
 112         setbits_be32 (&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
 113 #endif
 114
 115         return 0;
 116 }
 117
 118 int is_micron(void){
 119
 120         ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00);
 121         uchar macaddr[6];
 122         u32 brddate, macchk, ismicron;
 123
 124         /*
 125          * MAC address has serial number with date of manufacture
 126          * Boards made before Nov-08 #1180 use Micron memory;
 127          * 001e59 is the STx vendor #
 128          * Default is Elpida since it works for both but is slightly slower
 129          */
 130         ismicron = 0;
 131         if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) {
 132                 brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
 133                 macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
 134                 debug("brddate = %d\n\t", brddate);
 135
 136                 if (macchk == 0x001e59 && brddate <= 8111180)
 137                         ismicron = 1;
 138         } else if (brd_rev < 0x400) {
 139                 ismicron = 1;
 140         }
 141         debug("Using %s Memory settings\n\t",
 142                 ismicron ? "Micron" : "Elpida");
 143         return(ismicron);
 144 }
 145
 146 phys_size_t initdram(int board_type)
 147 {
 148         u32 msize = 0;
 149         /*
 150          * Elpida MDDRC and initialization settings are an alternative
 151          * to the Default Micron ones for all but the earliest Rev 4 boards
 152          */
 153         ddr512x_config_t elpida_mddrc_config = {
 154                 .ddr_sys_config   = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
 155                 .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
 156                 .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
 157                 .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
 158         };
 159
 160         u32 elpida_init_sequence[] = {
 161                 CONFIG_SYS_DDRCMD_NOP,
 162                 CONFIG_SYS_DDRCMD_NOP,
 163                 CONFIG_SYS_DDRCMD_NOP,
 164                 CONFIG_SYS_DDRCMD_NOP,
 165                 CONFIG_SYS_DDRCMD_NOP,
 166                 CONFIG_SYS_DDRCMD_NOP,
 167                 CONFIG_SYS_DDRCMD_NOP,
 168                 CONFIG_SYS_DDRCMD_NOP,
 169                 CONFIG_SYS_DDRCMD_NOP,
 170                 CONFIG_SYS_DDRCMD_NOP,
 171                 CONFIG_SYS_DDRCMD_PCHG_ALL,
 172                 CONFIG_SYS_DDRCMD_NOP,
 173                 CONFIG_SYS_DDRCMD_RFSH,
 174                 CONFIG_SYS_DDRCMD_NOP,
 175                 CONFIG_SYS_DDRCMD_RFSH,
 176                 CONFIG_SYS_DDRCMD_NOP,
 177                 CONFIG_SYS_DDRCMD_EM2,
 178                 CONFIG_SYS_DDRCMD_EM3,
 179                 CONFIG_SYS_DDRCMD_EN_DLL,
 180                 CONFIG_SYS_ELPIDA_RES_DLL,
 181                 CONFIG_SYS_DDRCMD_PCHG_ALL,
 182                 CONFIG_SYS_DDRCMD_RFSH,
 183                 CONFIG_SYS_DDRCMD_RFSH,
 184                 CONFIG_SYS_DDRCMD_RFSH,
 185                 CONFIG_SYS_ELPIDA_INIT_DEV_OP,
 186                 CONFIG_SYS_DDRCMD_NOP,
 187                 CONFIG_SYS_DDRCMD_NOP,
 188                 CONFIG_SYS_DDRCMD_NOP,
 189                 CONFIG_SYS_DDRCMD_NOP,
 190                 CONFIG_SYS_DDRCMD_NOP,
 191                 CONFIG_SYS_DDRCMD_NOP,
 192                 CONFIG_SYS_DDRCMD_NOP,
 193                 CONFIG_SYS_DDRCMD_NOP,
 194                 CONFIG_SYS_DDRCMD_NOP,
 195                 CONFIG_SYS_DDRCMD_NOP,
 196                 CONFIG_SYS_DDRCMD_OCD_DEFAULT,
 197                 CONFIG_SYS_ELPIDA_OCD_EXIT,
 198                 CONFIG_SYS_DDRCMD_NOP,
 199                 CONFIG_SYS_DDRCMD_NOP,
 200                 CONFIG_SYS_DDRCMD_NOP,
 201                 CONFIG_SYS_DDRCMD_NOP,
 202                 CONFIG_SYS_DDRCMD_NOP,
 203                 CONFIG_SYS_DDRCMD_NOP,
 204                 CONFIG_SYS_DDRCMD_NOP,
 205                 CONFIG_SYS_DDRCMD_NOP,
 206                 CONFIG_SYS_DDRCMD_NOP,
 207                 CONFIG_SYS_DDRCMD_NOP
 208         };
 209
 210         if (is_micron()) {
 211                 msize = fixed_sdram(NULL, NULL, 0);
 212         } else {
 213                 msize = fixed_sdram(&elpida_mddrc_config,
 214                                 elpida_init_sequence,
 215                                 sizeof(elpida_init_sequence)/sizeof(u32));
 216         }
 217
 218         return msize;
 219 }
 220
 221 int misc_init_r(void)
 222 {
 223         u8 tmp_val;
 224
 225         /* Using this for DIU init before the driver in linux takes over
 226          *  Enable the TFP410 Encoder (I2C address 0x38)
 227          */
 228
 229         i2c_set_bus_num(2);
 230         tmp_val = 0xBF;
 231         i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
 232         /* Verify if enabled */
 233         tmp_val = 0;
 234         i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
 235         debug("DVI Encoder Read: 0x%02x\n", tmp_val);
 236
 237         tmp_val = 0x10;
 238         i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
 239         /* Verify if enabled */
 240         tmp_val = 0;
 241         i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
 242         debug("DVI Encoder Read: 0x%02x\n", tmp_val);
 243
 244         return 0;
 245 }
 246
 247 static  iopin_t ioregs_init[] = {
 248         /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
 249         {
 250                 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
 251                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 252                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 253         },
 254         /* Set highest Slew on 9 PATA pins */
 255         {
 256                 offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
 257                 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 258                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 259         },
 260         /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
 261         {
 262                 offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
 263                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 264                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 265         },
 266         /* FUNC1=SPDIF_TXCLK */
 267         {
 268                 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
 269                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 270                 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 271         },
 272         /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
 273         {
 274                 offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
 275                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 276                 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 277         },
 278         /* FUNC2=DIU CLK */
 279         {
 280                 offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
 281                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 282                 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 283         },
 284         /* FUNC2=DIU_HSYNC */
 285         {
 286                 offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
 287                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 288                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 289         },
 290         /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
 291         {
 292                 offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
 293                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 294                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 295         }
 296 };
 297
 298 static  iopin_t rev2_silicon_pci_ioregs_init[] = {
 299         /* FUNC0=PCI Sets next 54 to PCI pads */
 300         {
 301                 offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
 302                 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
 303         }
 304 };
 305
 306 int checkboard (void)
 307 {
 308         ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
 309         uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
 310         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 311         u32 spridr = in_be32(&im->sysconf.spridr);
 312
 313         printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
 314                 brd_rev, cpld_rev);
 315
 316         /* initialize function mux & slew rate IO inter alia on IO Pins  */
 317         iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
 318
 319         if (SVR_MJREV (spridr) >= 2)
 320                 iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
 321
 322         return 0;
 323 }
 324
 325 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 326 void ft_board_setup(void *blob, bd_t *bd)
 327 {
 328         ft_cpu_setup(blob, bd);
 329 }
 330 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */