2 * (C) Copyright 2007-2009 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/bitops.h>
28 #include <asm/processor.h>
29 #include <asm/mpc512x.h>
30 #include <fdt_support.h>
31 #ifdef CONFIG_MISC_INIT_R
36 #include <linux/mtd/mtd.h>
37 #include <linux/mtd/nand.h>
39 DECLARE_GLOBAL_DATA_PTR
;
42 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
43 CLOCK_SCCR1_DDR_EN | \
44 CLOCK_SCCR1_FEC_EN | \
45 CLOCK_SCCR1_LPC_EN | \
46 CLOCK_SCCR1_NFC_EN | \
47 CLOCK_SCCR1_PATA_EN | \
48 CLOCK_SCCR1_PCI_EN | \
49 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
50 CLOCK_SCCR1_PSCFIFO_EN | \
53 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \
54 CLOCK_SCCR2_I2C_EN | \
55 CLOCK_SCCR2_MEM_EN | \
56 CLOCK_SCCR2_SPDIF_EN | \
57 CLOCK_SCCR2_USB1_EN | \
60 void __mpc5121_nfc_select_chip(struct mtd_info
*mtd
, int chip
);
62 /* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
63 extern int mpc5121_nfc_chip
;
65 /* Control chips select signal on MPC5121ADS board */
66 void mpc5121_nfc_select_chip(struct mtd_info
*mtd
, int chip
)
68 unsigned char *csreg
= (u8
*)CONFIG_SYS_CPLD_BASE
+ 0x09;
75 __mpc5121_nfc_select_chip(mtd
, 0);
76 v
&= ~(1 << mpc5121_nfc_chip
);
78 __mpc5121_nfc_select_chip(mtd
, -1);
84 int board_early_init_f(void)
86 volatile immap_t
*im
= (immap_t
*) CONFIG_SYS_IMMR
;
90 * Initialize Local Window for the CPLD registers access (CS2 selects
93 out_be32(&im
->sysconf
.lpcs2aw
,
94 CSAW_START(CONFIG_SYS_CPLD_BASE
) |
95 CSAW_STOP(CONFIG_SYS_CPLD_BASE
, CONFIG_SYS_CPLD_SIZE
)
97 out_be32(&im
->lpc
.cs_cfg
[2], CONFIG_SYS_CS2_CFG
);
98 sync_law(&im
->sysconf
.lpcs2aw
);
101 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
103 * Without this the flash identification routine fails, as it needs to issue
104 * write commands in order to establish the device ID.
107 #ifdef CONFIG_MPC5121ADS_REV2
108 out_8((u8
*)(CONFIG_SYS_CPLD_BASE
+ 0x08), 0xC1);
110 if (in_8((u8
*)(CONFIG_SYS_CPLD_BASE
+ 0x08)) & 0x04) {
111 out_8((u8
*)(CONFIG_SYS_CPLD_BASE
+ 0x08), 0xC1);
113 /* running from Backup flash */
114 out_8((u8
*)(CONFIG_SYS_CPLD_BASE
+ 0x08), 0x32);
118 * Configure Flash Speed
120 out_be32(&im
->lpc
.cs_cfg
[0], CONFIG_SYS_CS0_CFG
);
122 spridr
= in_be32(&im
->sysconf
.spridr
);
124 if (SVR_MJREV (spridr
) >= 2)
125 out_be32 (&im
->lpc
.altr
, CONFIG_SYS_CS_ALETIMING
);
130 out_be32 (&im
->clk
.sccr
[0], SCCR1_CLOCKS_EN
);
131 out_be32 (&im
->clk
.sccr
[1], SCCR2_CLOCKS_EN
);
132 #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
133 setbits_be32 (&im
->clk
.sccr
[1], CLOCK_SCCR2_IIM_EN
);
141 ushort brd_rev
= *(vu_short
*)(CONFIG_SYS_CPLD_BASE
+ 0x00);
143 u32 brddate
, macchk
, ismicron
;
146 * MAC address has serial number with date of manufacture
147 * Boards made before Nov-08 #1180 use Micron memory;
148 * 001e59 is the STx vendor #
149 * Default is Elpida since it works for both but is slightly slower
152 if (brd_rev
>= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr
)) {
153 brddate
= (macaddr
[3] << 16) + (macaddr
[4] << 8) + macaddr
[5];
154 macchk
= (macaddr
[0] << 16) + (macaddr
[1] << 8) + macaddr
[2];
155 debug("brddate = %d\n\t", brddate
);
157 if (macchk
== 0x001e59 && brddate
<= 8111180)
159 } else if (brd_rev
< 0x400) {
162 debug("Using %s Memory settings\n\t",
163 ismicron
? "Micron" : "Elpida");
167 phys_size_t
initdram(int board_type
)
171 * Elpida MDDRC and initialization settings are an alternative
172 * to the Default Micron ones for all but the earliest Rev 4 boards
174 ddr512x_config_t elpida_mddrc_config
= {
175 .ddr_sys_config
= CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA
,
176 .ddr_time_config0
= CONFIG_SYS_MDDRC_TIME_CFG0
,
177 .ddr_time_config1
= CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA
,
178 .ddr_time_config2
= CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA
,
181 u32 elpida_init_sequence
[] = {
182 CONFIG_SYS_DDRCMD_NOP
,
183 CONFIG_SYS_DDRCMD_NOP
,
184 CONFIG_SYS_DDRCMD_NOP
,
185 CONFIG_SYS_DDRCMD_NOP
,
186 CONFIG_SYS_DDRCMD_NOP
,
187 CONFIG_SYS_DDRCMD_NOP
,
188 CONFIG_SYS_DDRCMD_NOP
,
189 CONFIG_SYS_DDRCMD_NOP
,
190 CONFIG_SYS_DDRCMD_NOP
,
191 CONFIG_SYS_DDRCMD_NOP
,
192 CONFIG_SYS_DDRCMD_PCHG_ALL
,
193 CONFIG_SYS_DDRCMD_NOP
,
194 CONFIG_SYS_DDRCMD_RFSH
,
195 CONFIG_SYS_DDRCMD_NOP
,
196 CONFIG_SYS_DDRCMD_RFSH
,
197 CONFIG_SYS_DDRCMD_NOP
,
198 CONFIG_SYS_DDRCMD_EM2
,
199 CONFIG_SYS_DDRCMD_EM3
,
200 CONFIG_SYS_DDRCMD_EN_DLL
,
201 CONFIG_SYS_ELPIDA_RES_DLL
,
202 CONFIG_SYS_DDRCMD_PCHG_ALL
,
203 CONFIG_SYS_DDRCMD_RFSH
,
204 CONFIG_SYS_DDRCMD_RFSH
,
205 CONFIG_SYS_DDRCMD_RFSH
,
206 CONFIG_SYS_ELPIDA_INIT_DEV_OP
,
207 CONFIG_SYS_DDRCMD_NOP
,
208 CONFIG_SYS_DDRCMD_NOP
,
209 CONFIG_SYS_DDRCMD_NOP
,
210 CONFIG_SYS_DDRCMD_NOP
,
211 CONFIG_SYS_DDRCMD_NOP
,
212 CONFIG_SYS_DDRCMD_NOP
,
213 CONFIG_SYS_DDRCMD_NOP
,
214 CONFIG_SYS_DDRCMD_NOP
,
215 CONFIG_SYS_DDRCMD_NOP
,
216 CONFIG_SYS_DDRCMD_NOP
,
217 CONFIG_SYS_DDRCMD_OCD_DEFAULT
,
218 CONFIG_SYS_ELPIDA_OCD_EXIT
,
219 CONFIG_SYS_DDRCMD_NOP
,
220 CONFIG_SYS_DDRCMD_NOP
,
221 CONFIG_SYS_DDRCMD_NOP
,
222 CONFIG_SYS_DDRCMD_NOP
,
223 CONFIG_SYS_DDRCMD_NOP
,
224 CONFIG_SYS_DDRCMD_NOP
,
225 CONFIG_SYS_DDRCMD_NOP
,
226 CONFIG_SYS_DDRCMD_NOP
,
227 CONFIG_SYS_DDRCMD_NOP
,
228 CONFIG_SYS_DDRCMD_NOP
232 msize
= fixed_sdram(NULL
, NULL
, 0);
234 msize
= fixed_sdram(&elpida_mddrc_config
,
235 elpida_init_sequence
,
236 sizeof(elpida_init_sequence
)/sizeof(u32
));
242 int misc_init_r(void)
246 /* Using this for DIU init before the driver in linux takes over
247 * Enable the TFP410 Encoder (I2C address 0x38)
252 i2c_write(0x38, 0x08, 1, &tmp_val
, sizeof(tmp_val
));
253 /* Verify if enabled */
255 i2c_read(0x38, 0x08, 1, &tmp_val
, sizeof(tmp_val
));
256 debug("DVI Encoder Read: 0x%02lx\n", tmp_val
);
259 i2c_write(0x38, 0x0A, 1, &tmp_val
, sizeof(tmp_val
));
260 /* Verify if enabled */
262 i2c_read(0x38, 0x0A, 1, &tmp_val
, sizeof(tmp_val
));
263 debug("DVI Encoder Read: 0x%02lx\n", tmp_val
);
268 static iopin_t ioregs_init
[] = {
269 /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
271 offsetof(struct ioctrl512x
, io_control_spdif_txclk
), 3, 0,
272 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
273 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
275 /* Set highest Slew on 9 PATA pins */
277 offsetof(struct ioctrl512x
, io_control_pata_ce1
), 9, 1,
278 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
279 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
281 /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
283 offsetof(struct ioctrl512x
, io_control_psc0_0
), 15, 0,
284 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
285 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
287 /* FUNC1=SPDIF_TXCLK */
289 offsetof(struct ioctrl512x
, io_control_lpc_cs1
), 1, 0,
290 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
291 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
293 /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
295 offsetof(struct ioctrl512x
, io_control_i2c1_scl
), 2, 0,
296 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
297 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
301 offsetof(struct ioctrl512x
, io_control_psc6_0
), 1, 0,
302 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
303 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
305 /* FUNC2=DIU_HSYNC */
307 offsetof(struct ioctrl512x
, io_control_psc6_1
), 1, 0,
308 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
309 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
311 /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
313 offsetof(struct ioctrl512x
, io_control_psc6_4
), 26, 0,
314 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
315 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
319 static iopin_t rev2_silicon_pci_ioregs_init
[] = {
320 /* FUNC0=PCI Sets next 54 to PCI pads */
322 offsetof(struct ioctrl512x
, io_control_pci_ad31
), 54, 0,
323 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
327 int checkboard (void)
329 ushort brd_rev
= *(vu_short
*) (CONFIG_SYS_CPLD_BASE
+ 0x00);
330 uchar cpld_rev
= *(vu_char
*) (CONFIG_SYS_CPLD_BASE
+ 0x02);
331 volatile immap_t
*im
= (immap_t
*) CONFIG_SYS_IMMR
;
332 u32 spridr
= in_be32(&im
->sysconf
.spridr
);
334 printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
337 /* initialize function mux & slew rate IO inter alia on IO Pins */
338 iopin_initialize(ioregs_init
, ARRAY_SIZE(ioregs_init
));
340 if (SVR_MJREV (spridr
) >= 2)
341 iopin_initialize(rev2_silicon_pci_ioregs_init
, 1);
346 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
347 void ft_board_setup(void *blob
, bd_t
*bd
)
349 ft_cpu_setup(blob
, bd
);
351 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */