board/freescale/mpc8349emds/mpc8349emds.c

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  */
  24
  25 #include <common.h>
  26 #include <ioports.h>
  27 #include <mpc83xx.h>
  28 #include <asm/mpc8349_pci.h>
  29 #include <i2c.h>
  30 #include <spi.h>
  31 #include <miiphy.h>
  32 #include <spd_sdram.h>
  33
  34 #if defined(CONFIG_OF_LIBFDT)
  35 #include <libfdt.h>
  36 #endif
  37
  38 int fixed_sdram(void);
  39 void sdram_init(void);
  40
  41 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
  42 void ddr_enable_ecc(unsigned int dram_size);
  43 #endif
  44
  45 int board_early_init_f (void)
  46 {
  47         volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
  48
  49         /* Enable flash write */
  50         bcsr[1] &= ~0x01;
  51
  52 #ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
  53         /* Use USB PHY on SYS board */
  54         bcsr[5] |= 0x02;
  55 #endif
  56
  57         return 0;
  58 }
  59
  60 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
  61
  62 phys_size_t initdram (int board_type)
  63 {
  64         volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  65         u32 msize = 0;
  66
  67         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  68                 return -1;
  69
  70         /* DDR SDRAM - Main SODIMM */
  71         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
  72 #if defined(CONFIG_SPD_EEPROM)
  73         msize = spd_sdram();
  74 #else
  75         msize = fixed_sdram();
  76 #endif
  77         /*
  78          * Initialize SDRAM if it is on local bus.
  79          */
  80         sdram_init();
  81
  82 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  83         /*
  84          * Initialize and enable DDR ECC.
  85          */
  86         ddr_enable_ecc(msize * 1024 * 1024);
  87 #endif
  88
  89         /* return total bus SDRAM size(bytes)  -- DDR */
  90         return (msize * 1024 * 1024);
  91 }
  92
  93 #if !defined(CONFIG_SPD_EEPROM)
  94 /*************************************************************************
  95  *  fixed sdram init -- doesn't use serial presence detect.
  96  ************************************************************************/
  97 int fixed_sdram(void)
  98 {
  99         volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 100         u32 msize = 0;
 101         u32 ddr_size;
 102         u32 ddr_size_log2;
 103
 104         msize = CONFIG_SYS_DDR_SIZE;
 105         for (ddr_size = msize << 20, ddr_size_log2 = 0;
 106              (ddr_size > 1);
 107              ddr_size = ddr_size>>1, ddr_size_log2++) {
 108                 if (ddr_size & 1) {
 109                         return -1;
 110                 }
 111         }
 112         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
 113         im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 114
 115 #if (CONFIG_SYS_DDR_SIZE != 256)
 116 #warning Currenly any ddr size other than 256 is not supported
 117 #endif
 118 #ifdef CONFIG_DDR_II
 119         im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
 120         im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
 121         im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 122         im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 123         im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 124         im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 125         im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
 126         im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
 127         im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
 128         im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
 129         im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 130         im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 131 #else
 132         im->ddr.csbnds[2].csbnds = 0x0000000f;
 133         im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
 134
 135         /* currently we use only one CS, so disable the other banks */
 136         im->ddr.cs_config[0] = 0;
 137         im->ddr.cs_config[1] = 0;
 138         im->ddr.cs_config[3] = 0;
 139
 140         im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 141         im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 142
 143         im->ddr.sdram_cfg =
 144                 SDRAM_CFG_SREN
 145 #if defined(CONFIG_DDR_2T_TIMING)
 146                 | SDRAM_CFG_2T_EN
 147 #endif
 148                 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
 149 #if defined (CONFIG_DDR_32BIT)
 150         /* for 32-bit mode burst length is 8 */
 151         im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
 152 #endif
 153         im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
 154
 155         im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 156 #endif
 157         udelay(200);
 158
 159         /* enable DDR controller */
 160         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 161         return msize;
 162 }
 163 #endif/*!CONFIG_SYS_SPD_EEPROM*/
 164
 165
 166 int checkboard (void)
 167 {
 168         /*
 169          * Warning: do not read the BCSR registers here
 170          *
 171          * There is a timing bug in the 8349E and 8349EA BCSR code
 172          * version 1.2 (read from BCSR 11) that will cause the CFI
 173          * flash initialization code to overwrite BCSR 0, disabling
 174          * the serial ports and gigabit ethernet
 175          */
 176
 177         puts("Board: Freescale MPC8349EMDS\n");
 178         return 0;
 179 }
 180
 181 /*
 182  * if MPC8349EMDS is soldered with SDRAM
 183  */
 184 #if defined(CONFIG_SYS_BR2_PRELIM)  \
 185         && defined(CONFIG_SYS_OR2_PRELIM) \
 186         && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
 187         && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
 188 /*
 189  * Initialize SDRAM memory on the Local Bus.
 190  */
 191
 192 void sdram_init(void)
 193 {
 194         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 195         volatile fsl_lbc_t *lbc = &immap->im_lbc;
 196         uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 197
 198         /*
 199          * Setup SDRAM Base and Option Registers, already done in cpu_init.c
 200          */
 201
 202         /* setup mtrpt, lsrt and lbcr for LB bus */
 203         lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 204         lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 205         lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 206         asm("sync");
 207
 208         /*
 209          * Configure the SDRAM controller Machine Mode Register.
 210          */
 211         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
 212
 213         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
 214         asm("sync");
 215         *sdram_addr = 0xff;
 216         udelay(100);
 217
 218         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
 219         asm("sync");
 220         /*1 times*/
 221         *sdram_addr = 0xff;
 222         udelay(100);
 223         /*2 times*/
 224         *sdram_addr = 0xff;
 225         udelay(100);
 226         /*3 times*/
 227         *sdram_addr = 0xff;
 228         udelay(100);
 229         /*4 times*/
 230         *sdram_addr = 0xff;
 231         udelay(100);
 232         /*5 times*/
 233         *sdram_addr = 0xff;
 234         udelay(100);
 235         /*6 times*/
 236         *sdram_addr = 0xff;
 237         udelay(100);
 238         /*7 times*/
 239         *sdram_addr = 0xff;
 240         udelay(100);
 241         /*8 times*/
 242         *sdram_addr = 0xff;
 243         udelay(100);
 244
 245         /* 0x58636733; mode register write operation */
 246         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
 247         asm("sync");
 248         *sdram_addr = 0xff;
 249         udelay(100);
 250
 251         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
 252         asm("sync");
 253         *sdram_addr = 0xff;
 254         udelay(100);
 255 }
 256 #else
 257 void sdram_init(void)
 258 {
 259 }
 260 #endif
 261
 262 /*
 263  * The following are used to control the SPI chip selects for the SPI command.
 264  */
 265 #ifdef CONFIG_MPC8XXX_SPI
 266
 267 #define SPI_CS_MASK     0x80000000
 268
 269 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 270 {
 271         return bus == 0 && cs == 0;
 272 }
 273
 274 void spi_cs_activate(struct spi_slave *slave)
 275 {
 276         volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
 277
 278         iopd->dat &= ~SPI_CS_MASK;
 279 }
 280
 281 void spi_cs_deactivate(struct spi_slave *slave)
 282 {
 283         volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
 284
 285         iopd->dat |=  SPI_CS_MASK;
 286 }
 287 #endif /* CONFIG_HARD_SPI */
 288
 289 #if defined(CONFIG_OF_BOARD_SETUP)
 290 void ft_board_setup(void *blob, bd_t *bd)
 291 {
 292         ft_cpu_setup(blob, bd);
 293 #ifdef CONFIG_PCI
 294         ft_pci_setup(blob, bd);
 295 #endif
 296 }
 297 #endif