board/freescale/mpc8360emds/mpc8360emds.c

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  * Dave Liu <daveliu@freescale.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  */
  13
  14 #include <common.h>
  15 #include <ioports.h>
  16 #include <mpc83xx.h>
  17 #include <i2c.h>
  18 #include <miiphy.h>
  19 #if defined(CONFIG_PCI)
  20 #include <pci.h>
  21 #endif
  22 #include <spd_sdram.h>
  23 #include <asm/mmu.h>
  24 #if defined(CONFIG_OF_LIBFDT)
  25 #include <libfdt.h>
  26 #endif
  27 #if defined(CONFIG_PQ_MDS_PIB)
  28 #include "../common/pq-mds-pib.h"
  29 #endif
  30
  31 const qe_iop_conf_t qe_iop_conf_tab[] = {
  32         /* GETH1 */
  33         {0,  3, 1, 0, 1}, /* TxD0 */
  34         {0,  4, 1, 0, 1}, /* TxD1 */
  35         {0,  5, 1, 0, 1}, /* TxD2 */
  36         {0,  6, 1, 0, 1}, /* TxD3 */
  37         {1,  6, 1, 0, 3}, /* TxD4 */
  38         {1,  7, 1, 0, 1}, /* TxD5 */
  39         {1,  9, 1, 0, 2}, /* TxD6 */
  40         {1, 10, 1, 0, 2}, /* TxD7 */
  41         {0,  9, 2, 0, 1}, /* RxD0 */
  42         {0, 10, 2, 0, 1}, /* RxD1 */
  43         {0, 11, 2, 0, 1}, /* RxD2 */
  44         {0, 12, 2, 0, 1}, /* RxD3 */
  45         {0, 13, 2, 0, 1}, /* RxD4 */
  46         {1,  1, 2, 0, 2}, /* RxD5 */
  47         {1,  0, 2, 0, 2}, /* RxD6 */
  48         {1,  4, 2, 0, 2}, /* RxD7 */
  49         {0,  7, 1, 0, 1}, /* TX_EN */
  50         {0,  8, 1, 0, 1}, /* TX_ER */
  51         {0, 15, 2, 0, 1}, /* RX_DV */
  52         {0, 16, 2, 0, 1}, /* RX_ER */
  53         {0,  0, 2, 0, 1}, /* RX_CLK */
  54         {2,  9, 1, 0, 3}, /* GTX_CLK - CLK10 */
  55         {2,  8, 2, 0, 1}, /* GTX125 - CLK9 */
  56         /* GETH2 */
  57         {0, 17, 1, 0, 1}, /* TxD0 */
  58         {0, 18, 1, 0, 1}, /* TxD1 */
  59         {0, 19, 1, 0, 1}, /* TxD2 */
  60         {0, 20, 1, 0, 1}, /* TxD3 */
  61         {1,  2, 1, 0, 1}, /* TxD4 */
  62         {1,  3, 1, 0, 2}, /* TxD5 */
  63         {1,  5, 1, 0, 3}, /* TxD6 */
  64         {1,  8, 1, 0, 3}, /* TxD7 */
  65         {0, 23, 2, 0, 1}, /* RxD0 */
  66         {0, 24, 2, 0, 1}, /* RxD1 */
  67         {0, 25, 2, 0, 1}, /* RxD2 */
  68         {0, 26, 2, 0, 1}, /* RxD3 */
  69         {0, 27, 2, 0, 1}, /* RxD4 */
  70         {1, 12, 2, 0, 2}, /* RxD5 */
  71         {1, 13, 2, 0, 3}, /* RxD6 */
  72         {1, 11, 2, 0, 2}, /* RxD7 */
  73         {0, 21, 1, 0, 1}, /* TX_EN */
  74         {0, 22, 1, 0, 1}, /* TX_ER */
  75         {0, 29, 2, 0, 1}, /* RX_DV */
  76         {0, 30, 2, 0, 1}, /* RX_ER */
  77         {0, 31, 2, 0, 1}, /* RX_CLK */
  78         {2,  2, 1, 0, 2}, /* GTX_CLK = CLK10 */
  79         {2,  3, 2, 0, 1}, /* GTX125 - CLK4 */
  80
  81         {0,  1, 3, 0, 2}, /* MDIO */
  82         {0,  2, 1, 0, 1}, /* MDC */
  83
  84         {5,  0, 1, 0, 2}, /* UART2_SOUT */
  85         {5,  1, 2, 0, 3}, /* UART2_CTS */
  86         {5,  2, 1, 0, 1}, /* UART2_RTS */
  87         {5,  3, 2, 0, 2}, /* UART2_SIN */
  88
  89         {0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
  90 };
  91
  92 int board_early_init_f(void)
  93 {
  94
  95         u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
  96         const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  97
  98         /* Enable flash write */
  99         bcsr[0xa] &= ~0x04;
 100
 101         /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
 102         if (REVID_MAJOR(immr->sysconf.spridr) == 2)
 103                 bcsr[0xe] = 0x30;
 104
 105         /* Enable second UART */
 106         bcsr[0x9] &= ~0x01;
 107
 108         return 0;
 109 }
 110
 111 int board_early_init_r(void)
 112 {
 113 #ifdef CONFIG_PQ_MDS_PIB
 114         pib_init();
 115 #endif
 116         return 0;
 117 }
 118
 119 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 120 extern void ddr_enable_ecc(unsigned int dram_size);
 121 #endif
 122 int fixed_sdram(void);
 123 static int sdram_init(unsigned int base);
 124
 125 phys_size_t initdram(int board_type)
 126 {
 127         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 128         u32 msize = 0;
 129
 130         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 131                 return -1;
 132
 133         /* DDR SDRAM - Main SODIMM */
 134         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 135 #if defined(CONFIG_SPD_EEPROM)
 136         msize = spd_sdram();
 137 #else
 138         msize = fixed_sdram();
 139 #endif
 140
 141 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 142         /*
 143          * Initialize DDR ECC byte
 144          */
 145         ddr_enable_ecc(msize * 1024 * 1024);
 146 #endif
 147         /*
 148          * Initialize SDRAM if it is on local bus.
 149          */
 150         msize += sdram_init(msize * 1024 * 1024);
 151
 152         /* return total bus SDRAM size(bytes)  -- DDR */
 153         return (msize * 1024 * 1024);
 154 }
 155
 156 #if !defined(CONFIG_SPD_EEPROM)
 157 /*************************************************************************
 158  *  fixed sdram init -- doesn't use serial presence detect.
 159  ************************************************************************/
 160 int fixed_sdram(void)
 161 {
 162         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 163         u32 msize = 0;
 164         u32 ddr_size;
 165         u32 ddr_size_log2;
 166
 167         msize = CONFIG_SYS_DDR_SIZE;
 168         for (ddr_size = msize << 20, ddr_size_log2 = 0;
 169              (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
 170                 if (ddr_size & 1) {
 171                         return -1;
 172                 }
 173         }
 174         im->sysconf.ddrlaw[0].ar =
 175             LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 176 #if (CONFIG_SYS_DDR_SIZE != 256)
 177 #warning Currenly any ddr size other than 256 is not supported
 178 #endif
 179 #ifdef CONFIG_DDR_II
 180         im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
 181         im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 182         im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 183         im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 184         im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 185         im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 186         im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
 187         im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
 188         im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
 189         im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
 190         im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 191         im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 192 #else
 193         im->ddr.csbnds[0].csbnds = 0x00000007;
 194         im->ddr.csbnds[1].csbnds = 0x0008000f;
 195
 196         im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
 197         im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG;
 198
 199         im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 200         im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 201         im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 202
 203         im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
 204         im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 205 #endif
 206         udelay(200);
 207         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 208
 209         return msize;
 210 }
 211 #endif                          /*!CONFIG_SYS_SPD_EEPROM */
 212
 213 int checkboard(void)
 214 {
 215         puts("Board: Freescale MPC8360EMDS\n");
 216         return 0;
 217 }
 218
 219 /*
 220  * if MPC8360EMDS is soldered with SDRAM
 221  */
 222 #ifdef CONFIG_SYS_LB_SDRAM
 223 /*
 224  * Initialize SDRAM memory on the Local Bus.
 225  */
 226
 227 static int sdram_init(unsigned int base)
 228 {
 229         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 230         volatile fsl_lbus_t *lbc = &immap->lbus;
 231         const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
 232         int rem = base % sdram_size;
 233         uint *sdram_addr;
 234
 235         /* window base address should be aligned to the window size */
 236         if (rem)
 237                 base = base - rem + sdram_size;
 238
 239         sdram_addr = (uint *)base;
 240         /*
 241          * Setup SDRAM Base and Option Registers
 242          */
 243         immap->lbus.bank[2].br = base | CONFIG_SYS_BR2;
 244         immap->lbus.bank[2].or = CONFIG_SYS_OR2;
 245         immap->sysconf.lblaw[2].bar = base;
 246         immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
 247
 248         /*setup mtrpt, lsrt and lbcr for LB bus */
 249         lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 250         lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 251         lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 252         asm("sync");
 253
 254         /*
 255          * Configure the SDRAM controller Machine Mode Register.
 256          */
 257         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;    /* Normal Operation */
 258         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;    /* Precharge All Banks */
 259         asm("sync");
 260         *sdram_addr = 0xff;
 261         udelay(100);
 262
 263         /*
 264          * We need do 8 times auto refresh operation.
 265          */
 266         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
 267         asm("sync");
 268         *sdram_addr = 0xff;     /* 1 times */
 269         udelay(100);
 270         *sdram_addr = 0xff;     /* 2 times */
 271         udelay(100);
 272         *sdram_addr = 0xff;     /* 3 times */
 273         udelay(100);
 274         *sdram_addr = 0xff;     /* 4 times */
 275         udelay(100);
 276         *sdram_addr = 0xff;     /* 5 times */
 277         udelay(100);
 278         *sdram_addr = 0xff;     /* 6 times */
 279         udelay(100);
 280         *sdram_addr = 0xff;     /* 7 times */
 281         udelay(100);
 282         *sdram_addr = 0xff;     /* 8 times */
 283         udelay(100);
 284
 285         /* Mode register write operation */
 286         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
 287         asm("sync");
 288         *(sdram_addr + 0xcc) = 0xff;
 289         udelay(100);
 290
 291         /* Normal operation */
 292         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
 293         asm("sync");
 294         *sdram_addr = 0xff;
 295         udelay(100);
 296
 297         /*
 298          * In non-aligned case we don't [normally] use that memory because
 299          * there is a hole.
 300          */
 301         if (rem)
 302                 return 0;
 303         return CONFIG_SYS_LBC_SDRAM_SIZE;
 304 }
 305 #else
 306 static int sdram_init(unsigned int base) { return 0; }
 307 #endif
 308
 309 #if defined(CONFIG_OF_BOARD_SETUP)
 310 void ft_board_setup(void *blob, bd_t *bd)
 311 {
 312         const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 313
 314         ft_cpu_setup(blob, bd);
 315 #ifdef CONFIG_PCI
 316         ft_pci_setup(blob, bd);
 317 #endif
 318         /*
 319          * mpc8360ea pb mds errata 2: RGMII timing
 320          * if on mpc8360ea rev. 2.1,
 321          * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
 322          */
 323         if ((REVID_MAJOR(immr->sysconf.spridr) == 2) &&
 324             (REVID_MINOR(immr->sysconf.spridr) == 1)) {
 325                 int nodeoffset;
 326                 const char *prop;
 327                 int path;
 328
 329                 nodeoffset = fdt_path_offset(blob, "/aliases");
 330                 if (nodeoffset >= 0) {
 331 #if defined(CONFIG_HAS_ETH0)
 332                         /* fixup UCC 1 if using rgmii-id mode */
 333                         prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
 334                         if (prop) {
 335                                 path = fdt_path_offset(blob, prop);
 336                                 prop = fdt_getprop(blob, path,
 337                                                    "phy-connection-type", 0);
 338                                 if (prop && (strcmp(prop, "rgmii-id") == 0))
 339                                         fdt_setprop(blob, path,
 340                                                     "phy-connection-type",
 341                                                     "rgmii-rxid",
 342                                                     sizeof("rgmii-rxid"));
 343                         }
 344 #endif
 345 #if defined(CONFIG_HAS_ETH1)
 346                         /* fixup UCC 2 if using rgmii-id mode */
 347                         prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
 348                         if (prop) {
 349                                 path = fdt_path_offset(blob, prop);
 350                                 prop = fdt_getprop(blob, path,
 351                                                    "phy-connection-type", 0);
 352                                 if (prop && (strcmp(prop, "rgmii-id") == 0))
 353                                         fdt_setprop(blob, path,
 354                                                     "phy-connection-type",
 355                                                     "rgmii-rxid",
 356                                                     sizeof("rgmii-rxid"));
 357                         }
 358 #endif
 359                 }
 360         }
 361 }
 362 #endif