board/freescale/mpc8360erdk/mpc8360erdk.c

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *                    Dave Liu <daveliu@freescale.com>
   4  *
   5  * Copyright (C) 2007 Logic Product Development, Inc.
   6  *                    Peter Barada <peterb@logicpd.com>
   7  *
   8  * Copyright (C) 2007 MontaVista Software, Inc.
   9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <common.h>
  15 #include <ioports.h>
  16 #include <mpc83xx.h>
  17 #include <i2c.h>
  18 #include <miiphy.h>
  19 #include <asm/io.h>
  20 #include <asm/mmu.h>
  21 #include <pci.h>
  22 #include <libfdt.h>
  23
  24 const qe_iop_conf_t qe_iop_conf_tab[] = {
  25         /* MDIO */
  26         {0,  1, 3, 0, 2}, /* MDIO */
  27         {0,  2, 1, 0, 1}, /* MDC */
  28
  29         /* UCC1 - UEC (Gigabit) */
  30         {0,  3, 1, 0, 1}, /* TxD0 */
  31         {0,  4, 1, 0, 1}, /* TxD1 */
  32         {0,  5, 1, 0, 1}, /* TxD2 */
  33         {0,  6, 1, 0, 1}, /* TxD3 */
  34         {0,  9, 2, 0, 1}, /* RxD0 */
  35         {0, 10, 2, 0, 1}, /* RxD1 */
  36         {0, 11, 2, 0, 1}, /* RxD2 */
  37         {0, 12, 2, 0, 1}, /* RxD3 */
  38         {0,  7, 1, 0, 1}, /* TX_EN */
  39         {0,  8, 1, 0, 1}, /* TX_ER */
  40         {0, 15, 2, 0, 1}, /* RX_DV */
  41         {0,  0, 2, 0, 1}, /* RX_CLK */
  42         {2,  9, 1, 0, 3}, /* GTX_CLK - CLK10 */
  43         {2,  8, 2, 0, 1}, /* GTX125 - CLK9 */
  44
  45         /* UCC2 - UEC (Gigabit) */
  46         {0, 17, 1, 0, 1}, /* TxD0 */
  47         {0, 18, 1, 0, 1}, /* TxD1 */
  48         {0, 19, 1, 0, 1}, /* TxD2 */
  49         {0, 20, 1, 0, 1}, /* TxD3 */
  50         {0, 23, 2, 0, 1}, /* RxD0 */
  51         {0, 24, 2, 0, 1}, /* RxD1 */
  52         {0, 25, 2, 0, 1}, /* RxD2 */
  53         {0, 26, 2, 0, 1}, /* RxD3 */
  54         {0, 21, 1, 0, 1}, /* TX_EN */
  55         {0, 22, 1, 0, 1}, /* TX_ER */
  56         {0, 29, 2, 0, 1}, /* RX_DV */
  57         {0, 31, 2, 0, 1}, /* RX_CLK */
  58         {2,  2, 1, 0, 2}, /* GTX_CLK - CLK10 */
  59         {2,  3, 2, 0, 1}, /* GTX125 - CLK4 */
  60
  61         /* UCC7 - UEC */
  62         {4,  0, 1, 0, 1}, /* TxD0 */
  63         {4,  1, 1, 0, 1}, /* TxD1 */
  64         {4,  2, 1, 0, 1}, /* TxD2 */
  65         {4,  3, 1, 0, 1}, /* TxD3 */
  66         {4,  6, 2, 0, 1}, /* RxD0 */
  67         {4,  7, 2, 0, 1}, /* RxD1 */
  68         {4,  8, 2, 0, 1}, /* RxD2 */
  69         {4,  9, 2, 0, 1}, /* RxD3 */
  70         {4,  4, 1, 0, 1}, /* TX_EN */
  71         {4,  5, 1, 0, 1}, /* TX_ER */
  72         {4, 12, 2, 0, 1}, /* RX_DV */
  73         {4, 13, 2, 0, 1}, /* RX_ER */
  74         {4, 10, 2, 0, 1}, /* COL */
  75         {4, 11, 2, 0, 1}, /* CRS */
  76         {2, 18, 2, 0, 1}, /* TX_CLK - CLK19 */
  77         {2, 19, 2, 0, 1}, /* RX_CLK - CLK20 */
  78
  79         /* UCC4 - UEC */
  80         {1, 14, 1, 0, 1}, /* TxD0 */
  81         {1, 15, 1, 0, 1}, /* TxD1 */
  82         {1, 16, 1, 0, 1}, /* TxD2 */
  83         {1, 17, 1, 0, 1}, /* TxD3 */
  84         {1, 20, 2, 0, 1}, /* RxD0 */
  85         {1, 21, 2, 0, 1}, /* RxD1 */
  86         {1, 22, 2, 0, 1}, /* RxD2 */
  87         {1, 23, 2, 0, 1}, /* RxD3 */
  88         {1, 18, 1, 0, 1}, /* TX_EN */
  89         {1, 19, 1, 0, 2}, /* TX_ER */
  90         {1, 26, 2, 0, 1}, /* RX_DV */
  91         {1, 27, 2, 0, 1}, /* RX_ER */
  92         {1, 24, 2, 0, 1}, /* COL */
  93         {1, 25, 2, 0, 1}, /* CRS */
  94         {2,  6, 2, 0, 1}, /* TX_CLK - CLK7 */
  95         {2,  7, 2, 0, 1}, /* RX_CLK - CLK8 */
  96
  97         /* PCI1 */
  98         {5,  4, 2, 0, 3}, /* PCI_M66EN */
  99         {5,  5, 1, 0, 3}, /* PCI_INTA */
 100         {5,  6, 1, 0, 3}, /* PCI_RSTO */
 101         {5,  7, 3, 0, 3}, /* PCI_C_BE0 */
 102         {5,  8, 3, 0, 3}, /* PCI_C_BE1 */
 103         {5,  9, 3, 0, 3}, /* PCI_C_BE2 */
 104         {5, 10, 3, 0, 3}, /* PCI_C_BE3 */
 105         {5, 11, 3, 0, 3}, /* PCI_PAR */
 106         {5, 12, 3, 0, 3}, /* PCI_FRAME */
 107         {5, 13, 3, 0, 3}, /* PCI_TRDY */
 108         {5, 14, 3, 0, 3}, /* PCI_IRDY */
 109         {5, 15, 3, 0, 3}, /* PCI_STOP */
 110         {5, 16, 3, 0, 3}, /* PCI_DEVSEL */
 111         {5, 17, 0, 0, 0}, /* PCI_IDSEL */
 112         {5, 18, 3, 0, 3}, /* PCI_SERR */
 113         {5, 19, 3, 0, 3}, /* PCI_PERR */
 114         {5, 20, 3, 0, 3}, /* PCI_REQ0 */
 115         {5, 21, 2, 0, 3}, /* PCI_REQ1 */
 116         {5, 22, 2, 0, 3}, /* PCI_GNT2 */
 117         {5, 23, 3, 0, 3}, /* PCI_GNT0 */
 118         {5, 24, 1, 0, 3}, /* PCI_GNT1 */
 119         {5, 25, 1, 0, 3}, /* PCI_GNT2 */
 120         {5, 26, 0, 0, 0}, /* PCI_CLK0 */
 121         {5, 27, 0, 0, 0}, /* PCI_CLK1 */
 122         {5, 28, 0, 0, 0}, /* PCI_CLK2 */
 123         {5, 29, 0, 0, 3}, /* PCI_SYNC_OUT */
 124         {6,  0, 3, 0, 3}, /* PCI_AD0 */
 125         {6,  1, 3, 0, 3}, /* PCI_AD1 */
 126         {6,  2, 3, 0, 3}, /* PCI_AD2 */
 127         {6,  3, 3, 0, 3}, /* PCI_AD3 */
 128         {6,  4, 3, 0, 3}, /* PCI_AD4 */
 129         {6,  5, 3, 0, 3}, /* PCI_AD5 */
 130         {6,  6, 3, 0, 3}, /* PCI_AD6 */
 131         {6,  7, 3, 0, 3}, /* PCI_AD7 */
 132         {6,  8, 3, 0, 3}, /* PCI_AD8 */
 133         {6,  9, 3, 0, 3}, /* PCI_AD9 */
 134         {6, 10, 3, 0, 3}, /* PCI_AD10 */
 135         {6, 11, 3, 0, 3}, /* PCI_AD11 */
 136         {6, 12, 3, 0, 3}, /* PCI_AD12 */
 137         {6, 13, 3, 0, 3}, /* PCI_AD13 */
 138         {6, 14, 3, 0, 3}, /* PCI_AD14 */
 139         {6, 15, 3, 0, 3}, /* PCI_AD15 */
 140         {6, 16, 3, 0, 3}, /* PCI_AD16 */
 141         {6, 17, 3, 0, 3}, /* PCI_AD17 */
 142         {6, 18, 3, 0, 3}, /* PCI_AD18 */
 143         {6, 19, 3, 0, 3}, /* PCI_AD19 */
 144         {6, 20, 3, 0, 3}, /* PCI_AD20 */
 145         {6, 21, 3, 0, 3}, /* PCI_AD21 */
 146         {6, 22, 3, 0, 3}, /* PCI_AD22 */
 147         {6, 23, 3, 0, 3}, /* PCI_AD23 */
 148         {6, 24, 3, 0, 3}, /* PCI_AD24 */
 149         {6, 25, 3, 0, 3}, /* PCI_AD25 */
 150         {6, 26, 3, 0, 3}, /* PCI_AD26 */
 151         {6, 27, 3, 0, 3}, /* PCI_AD27 */
 152         {6, 28, 3, 0, 3}, /* PCI_AD28 */
 153         {6, 29, 3, 0, 3}, /* PCI_AD29 */
 154         {6, 30, 3, 0, 3}, /* PCI_AD30 */
 155         {6, 31, 3, 0, 3}, /* PCI_AD31 */
 156
 157         /* NAND */
 158         {4, 18, 2, 0, 0}, /* NAND_RYnBY */
 159
 160         /* DUART - UART2 */
 161         {5,  0, 1, 0, 2}, /* UART2_SOUT */
 162         {5,  2, 1, 0, 1}, /* UART2_RTS */
 163         {5,  3, 2, 0, 2}, /* UART2_SIN */
 164         {5,  1, 2, 0, 3}, /* UART2_CTS */
 165
 166         /* UCC5 - UART3 */
 167         {3,  0, 1, 0, 1}, /* UART3_TX */
 168         {3,  4, 1, 0, 1}, /* UART3_RTS */
 169         {3,  6, 2, 0, 1}, /* UART3_RX */
 170         {3, 12, 2, 0, 0}, /* UART3_CTS */
 171         {3, 13, 2, 0, 0}, /* UCC5_CD */
 172
 173         /* UCC6 - UART4 */
 174         {3, 14, 1, 0, 1}, /* UART4_TX */
 175         {3, 18, 1, 0, 1}, /* UART4_RTS */
 176         {3, 20, 2, 0, 1}, /* UART4_RX */
 177         {3, 26, 2, 0, 0}, /* UART4_CTS */
 178         {3, 27, 2, 0, 0}, /* UCC6_CD */
 179
 180         /* Fujitsu MB86277 (MINT) graphics controller */
 181         {0, 30, 1, 0, 0}, /* nSRESET_GRAPHICS */
 182         {1,  5, 1, 0, 0}, /* nXRST_GRAPHICS */
 183         {1,  7, 1, 0, 0}, /* LVDS_BKLT_CTR */
 184         {2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */
 185
 186         /* AD7843 ADC/Touchscreen controller */
 187         {4, 14, 1, 0, 0}, /* SPI_nCS0 */
 188         {4, 28, 3, 0, 3}, /* SPI_MOSI */
 189         {4, 29, 3, 0, 3}, /* SPI_MISO */
 190         {4, 30, 3, 0, 3}, /* SPI_CLK */
 191
 192         /* Freescale QUICC Engine USB Host Controller (FHCI) */
 193         {1,  2, 1, 0, 3}, /* USBOE */
 194         {1,  3, 1, 0, 3}, /* USBTP */
 195         {1,  8, 1, 0, 1}, /* USBTN */
 196         {1,  9, 2, 1, 3}, /* USBRP */
 197         {1, 10, 2, 0, 3}, /* USBRXD */
 198         {1, 11, 2, 1, 3}, /* USBRN */
 199         {2, 20, 2, 0, 1}, /* CLK21 */
 200         {4, 20, 1, 0, 0}, /* SPEED */
 201         {4, 21, 1, 0, 0}, /* SUSPND */
 202
 203         /* END of table */
 204         {0,  0, 0, 0, QE_IOP_TAB_END},
 205 };
 206
 207 int board_early_init_r(void)
 208 {
 209         void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
 210         u32 val;
 211
 212         /*
 213          * Because of errata in the UCCs, we have to write to the reserved
 214          * registers to slow the clocks down.
 215          */
 216         val = in_be32(reg);
 217         /* UCC1 */
 218         val |= 0x00003000;
 219         /* UCC2 */
 220         val |= 0x0c000000;
 221         out_be32(reg, val);
 222
 223         return 0;
 224 }
 225
 226 int fixed_sdram(void)
 227 {
 228         volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 229         u32 msize = 0;
 230         u32 ddr_size;
 231         u32 ddr_size_log2;
 232
 233         msize = CONFIG_SYS_DDR_SIZE;
 234         for (ddr_size = msize << 20, ddr_size_log2 = 0;
 235              (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
 236                 if (ddr_size & 1)
 237                         return -1;
 238         }
 239
 240         im->sysconf.ddrlaw[0].ar =
 241             LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 242
 243         im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
 244         im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 245         im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 246         im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 247         im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 248         im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 249         im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
 250         im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
 251         im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
 252         im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
 253         im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 254         im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 255         udelay(200);
 256         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 257
 258         return msize;
 259 }
 260
 261 phys_size_t initdram(int board_type)
 262 {
 263 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 264         extern void ddr_enable_ecc(unsigned int dram_size);
 265 #endif
 266         volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 267         u32 msize = 0;
 268
 269         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 270                 return -1;
 271
 272         /* DDR SDRAM - Main SODIMM */
 273         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 274         msize = fixed_sdram();
 275
 276 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 277         /*
 278          * Initialize DDR ECC byte
 279          */
 280         ddr_enable_ecc(msize * 1024 * 1024);
 281 #endif
 282
 283         /* return total bus SDRAM size(bytes)  -- DDR */
 284         return (msize * 1024 * 1024);
 285 }
 286
 287 int checkboard(void)
 288 {
 289         puts("Board: Freescale/Logic MPC8360ERDK\n");
 290         return 0;
 291 }
 292
 293 static struct pci_region pci_regions[] = {
 294         {
 295                 .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
 296                 .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
 297                 .size = CONFIG_SYS_PCI1_MEM_SIZE,
 298                 .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH,
 299         },
 300         {
 301                 .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
 302                 .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
 303                 .size = CONFIG_SYS_PCI1_MMIO_SIZE,
 304                 .flags = PCI_REGION_MEM,
 305         },
 306         {
 307                 .bus_start = CONFIG_SYS_PCI1_IO_BASE,
 308                 .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
 309                 .size = CONFIG_SYS_PCI1_IO_SIZE,
 310                 .flags = PCI_REGION_IO,
 311         },
 312 };
 313
 314 void pci_init_board(void)
 315 {
 316         volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
 317         volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 318         volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
 319         struct pci_region *reg[] = { pci_regions, };
 320
 321 #if defined(CONFIG_PCI_33M)
 322         clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
 323                     OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
 324         printf("PCI clock is 33MHz\n");
 325 #else
 326         clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
 327         printf("PCI clock is 66MHz\n");
 328 #endif
 329
 330         udelay(2000);
 331
 332         /* Configure PCI Local Access Windows */
 333         pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 334         pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
 335
 336         pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 337         pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 338
 339         mpc83xx_pci_init(1, reg);
 340 }
 341
 342 #if defined(CONFIG_OF_BOARD_SETUP)
 343 void ft_board_setup(void *blob, bd_t *bd)
 344 {
 345         ft_cpu_setup(blob, bd);
 346         ft_pci_setup(blob, bd);
 347 }
 348 #endif