2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Kevin Lam <kevin.lam@freescale.com>
4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/fsl_mpc83xx_serdes.h>
14 #include <fdt_support.h>
15 #include <spd_sdram.h>
17 #include <fsl_esdhc.h>
19 DECLARE_GLOBAL_DATA_PTR
;
21 #if defined(CONFIG_SYS_DRAM_TEST)
25 uint
*pstart
= (uint
*) CONFIG_SYS_MEMTEST_START
;
26 uint
*pend
= (uint
*) CONFIG_SYS_MEMTEST_END
;
29 printf("Testing DRAM from 0x%08x to 0x%08x\n",
30 CONFIG_SYS_MEMTEST_START
,
31 CONFIG_SYS_MEMTEST_END
);
33 printf("DRAM test phase 1:\n");
34 for (p
= pstart
; p
< pend
; p
++)
37 for (p
= pstart
; p
< pend
; p
++) {
38 if (*p
!= 0xaaaaaaaa) {
39 printf("DRAM test fails at: %08x\n", (uint
) p
);
44 printf("DRAM test phase 2:\n");
45 for (p
= pstart
; p
< pend
; p
++)
48 for (p
= pstart
; p
< pend
; p
++) {
49 if (*p
!= 0x55555555) {
50 printf("DRAM test fails at: %08x\n", (uint
) p
);
55 printf("DRAM test passed.\n");
60 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
61 void ddr_enable_ecc(unsigned int dram_size
);
63 int fixed_sdram(void);
67 immap_t
*im
= (immap_t
*) CONFIG_SYS_IMMR
;
70 if ((im
->sysconf
.immrbar
& IMMRBAR_BASE_ADDR
) != (u32
) im
)
73 #if defined(CONFIG_SPD_EEPROM)
76 msize
= fixed_sdram();
79 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
80 /* Initialize DDR ECC byte */
81 ddr_enable_ecc(msize
* 1024 * 1024);
83 /* return total bus DDR size(bytes) */
84 gd
->ram_size
= msize
* 1024 * 1024;
89 #if !defined(CONFIG_SPD_EEPROM)
90 /*************************************************************************
91 * fixed sdram init -- doesn't use serial presence detect.
92 ************************************************************************/
95 immap_t
*im
= (immap_t
*) CONFIG_SYS_IMMR
;
96 u32 msize
= CONFIG_SYS_DDR_SIZE
* 1024 * 1024;
97 u32 msize_log2
= __ilog2(msize
);
99 im
->sysconf
.ddrlaw
[0].bar
= CONFIG_SYS_DDR_SDRAM_BASE
& 0xfffff000;
100 im
->sysconf
.ddrlaw
[0].ar
= LBLAWAR_EN
| (msize_log2
- 1);
102 im
->sysconf
.ddrcdr
= CONFIG_SYS_DDRCDR_VALUE
;
105 im
->ddr
.sdram_clk_cntl
= CONFIG_SYS_DDR_SDRAM_CLK_CNTL
;
108 im
->ddr
.csbnds
[0].csbnds
= CONFIG_SYS_DDR_CS0_BNDS
;
109 im
->ddr
.cs_config
[0] = CONFIG_SYS_DDR_CS0_CONFIG
;
112 im
->ddr
.timing_cfg_0
= CONFIG_SYS_DDR_TIMING_0
;
113 im
->ddr
.timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1
;
114 im
->ddr
.timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2
;
115 im
->ddr
.timing_cfg_3
= CONFIG_SYS_DDR_TIMING_3
;
116 im
->ddr
.sdram_cfg
= CONFIG_SYS_DDR_SDRAM_CFG
;
117 im
->ddr
.sdram_cfg2
= CONFIG_SYS_DDR_SDRAM_CFG2
;
118 im
->ddr
.sdram_mode
= CONFIG_SYS_DDR_MODE
;
119 im
->ddr
.sdram_mode2
= CONFIG_SYS_DDR_MODE2
;
120 im
->ddr
.sdram_interval
= CONFIG_SYS_DDR_INTERVAL
;
124 im
->ddr
.sdram_cfg
|= SDRAM_CFG_MEM_EN
;
126 return CONFIG_SYS_DDR_SIZE
;
128 #endif /*!CONFIG_SYS_SPD_EEPROM */
132 puts("Board: Freescale MPC837xERDB\n");
136 int board_early_init_f(void)
138 #ifdef CONFIG_FSL_SERDES
139 immap_t
*immr
= (immap_t
*)CONFIG_SYS_IMMR
;
140 u32 spridr
= in_be32(&immr
->sysconf
.spridr
);
142 /* we check only part num, and don't look for CPU revisions */
143 switch (PARTID_NO_E(spridr
)) {
145 fsl_setup_serdes(CONFIG_FSL_SERDES1
, FSL_SERDES_PROTO_SATA
,
146 FSL_SERDES_CLK_100
, FSL_SERDES_VDD_1V
);
147 fsl_setup_serdes(CONFIG_FSL_SERDES2
, FSL_SERDES_PROTO_PEX
,
148 FSL_SERDES_CLK_100
, FSL_SERDES_VDD_1V
);
151 fsl_setup_serdes(CONFIG_FSL_SERDES2
, FSL_SERDES_PROTO_PEX
,
152 FSL_SERDES_CLK_100
, FSL_SERDES_VDD_1V
);
155 fsl_setup_serdes(CONFIG_FSL_SERDES1
, FSL_SERDES_PROTO_SATA
,
156 FSL_SERDES_CLK_100
, FSL_SERDES_VDD_1V
);
157 fsl_setup_serdes(CONFIG_FSL_SERDES2
, FSL_SERDES_PROTO_SATA
,
158 FSL_SERDES_CLK_100
, FSL_SERDES_VDD_1V
);
161 printf("serdes not configured: unknown CPU part number: "
162 "%04x\n", spridr
>> 16);
165 #endif /* CONFIG_FSL_SERDES */
169 #ifdef CONFIG_FSL_ESDHC
170 int board_mmc_init(bd_t
*bd
)
172 struct immap __iomem
*im
= (struct immap __iomem
*)CONFIG_SYS_IMMR
;
173 char buffer
[HWCONFIG_BUFFER_SIZE
] = {0};
174 int esdhc_hwconfig_enabled
= 0;
176 if (getenv_f("hwconfig", buffer
, sizeof(buffer
)) > 0)
177 esdhc_hwconfig_enabled
= hwconfig_f("esdhc", buffer
);
179 if (esdhc_hwconfig_enabled
== 0)
182 clrsetbits_be32(&im
->sysconf
.sicrl
, SICRL_USB_B
, SICRL_USB_B_SD
);
183 clrsetbits_be32(&im
->sysconf
.sicrh
, SICRH_SPI
, SICRH_SPI_SD
);
185 return fsl_esdhc_mmc_init(bd
);
190 * Miscellaneous late-boot configurations
192 * If a VSC7385 microcode image is present, then upload it.
194 int misc_init_r(void)
198 #ifdef CONFIG_VSC7385_IMAGE
199 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE
,
200 CONFIG_VSC7385_IMAGE_SIZE
)) {
201 puts("Failure uploading VSC7385 microcode.\n");
209 #if defined(CONFIG_OF_BOARD_SETUP)
211 int ft_board_setup(void *blob
, bd_t
*bd
)
214 ft_pci_setup(blob
, bd
);
216 ft_cpu_setup(blob
, bd
);
217 fsl_fdt_fixup_dr_usb(blob
, bd
);
218 fdt_fixup_esdhc(blob
, bd
);
222 #endif /* CONFIG_OF_BOARD_SETUP */