board/freescale/mpc837xerdb/mpc837xerdb.c

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  * Kevin Lam <kevin.lam@freescale.com>
   4  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  */
  14
  15 #include <common.h>
  16 #include <i2c.h>
  17 #include <asm/io.h>
  18 #include <asm/fsl_serdes.h>
  19 #include <spd_sdram.h>
  20 #include <vsc7385.h>
  21
  22
  23 #if defined(CFG_DRAM_TEST)
  24 int
  25 testdram(void)
  26 {
  27         uint *pstart = (uint *) CFG_MEMTEST_START;
  28         uint *pend = (uint *) CFG_MEMTEST_END;
  29         uint *p;
  30
  31         printf("Testing DRAM from 0x%08x to 0x%08x\n",
  32                CFG_MEMTEST_START,
  33                CFG_MEMTEST_END);
  34
  35         printf("DRAM test phase 1:\n");
  36         for (p = pstart; p < pend; p++)
  37                 *p = 0xaaaaaaaa;
  38
  39         for (p = pstart; p < pend; p++) {
  40                 if (*p != 0xaaaaaaaa) {
  41                         printf("DRAM test fails at: %08x\n", (uint) p);
  42                         return 1;
  43                 }
  44         }
  45
  46         printf("DRAM test phase 2:\n");
  47         for (p = pstart; p < pend; p++)
  48                 *p = 0x55555555;
  49
  50         for (p = pstart; p < pend; p++) {
  51                 if (*p != 0x55555555) {
  52                         printf("DRAM test fails at: %08x\n", (uint) p);
  53                         return 1;
  54                 }
  55         }
  56
  57         printf("DRAM test passed.\n");
  58         return 0;
  59 }
  60 #endif
  61
  62 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
  63 void ddr_enable_ecc(unsigned int dram_size);
  64 #endif
  65 int fixed_sdram(void);
  66
  67 long int initdram(int board_type)
  68 {
  69         immap_t *im = (immap_t *) CFG_IMMR;
  70         u32 msize = 0;
  71
  72         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  73                 return -1;
  74
  75 #if defined(CONFIG_SPD_EEPROM)
  76         msize = spd_sdram();
  77 #else
  78         msize = fixed_sdram();
  79 #endif
  80
  81 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
  82         /* Initialize DDR ECC byte */
  83         ddr_enable_ecc(msize * 1024 * 1024);
  84 #endif
  85         /* return total bus DDR size(bytes) */
  86         return (msize * 1024 * 1024);
  87 }
  88
  89 #if !defined(CONFIG_SPD_EEPROM)
  90 /*************************************************************************
  91  *  fixed sdram init -- doesn't use serial presence detect.
  92  ************************************************************************/
  93 int fixed_sdram(void)
  94 {
  95         immap_t *im = (immap_t *) CFG_IMMR;
  96         u32 msize = CFG_DDR_SIZE * 1024 * 1024;
  97         u32 msize_log2 = __ilog2(msize);
  98
  99         im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
 100         im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 101
 102         im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
 103         udelay(50000);
 104
 105         im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
 106         udelay(1000);
 107
 108         im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
 109         im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
 110         udelay(1000);
 111
 112         im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
 113         im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
 114         im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
 115         im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
 116         im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
 117         im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
 118         im->ddr.sdram_mode = CFG_DDR_MODE;
 119         im->ddr.sdram_mode2 = CFG_DDR_MODE2;
 120         im->ddr.sdram_interval = CFG_DDR_INTERVAL;
 121         sync();
 122         udelay(1000);
 123
 124         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 125         udelay(2000);
 126         return CFG_DDR_SIZE;
 127 }
 128 #endif  /*!CFG_SPD_EEPROM */
 129
 130 int checkboard(void)
 131 {
 132         puts("Board: Freescale MPC837xERDB\n");
 133         return 0;
 134 }
 135
 136 int board_early_init_f(void)
 137 {
 138 #ifdef CONFIG_FSL_SERDES
 139         immap_t *immr = (immap_t *)CFG_IMMR;
 140         u32 spridr = in_be32(&immr->sysconf.spridr);
 141
 142         /* we check only part num, and don't look for CPU revisions */
 143         switch (spridr >> 16) {
 144         case SPR_8379E_REV10 >> 16:
 145         case SPR_8379_REV10 >> 16:
 146                 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
 147                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 148                 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
 149                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 150                 break;
 151         case SPR_8378E_REV10 >> 16:
 152         case SPR_8378_REV10 >> 16:
 153                 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
 154                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 155                 break;
 156         case SPR_8377E_REV10 >> 16:
 157         case SPR_8377_REV10 >> 16:
 158                 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
 159                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 160                 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
 161                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 162                 break;
 163         default:
 164                 printf("serdes not configured: unknown CPU part number: "
 165                        "%04x\n", spridr >> 16);
 166                 break;
 167         }
 168 #endif /* CONFIG_FSL_SERDES */
 169         return 0;
 170 }
 171
 172 /*
 173  * Miscellaneous late-boot configurations
 174  *
 175  * If a VSC7385 microcode image is present, then upload it.
 176 */
 177 int misc_init_r(void)
 178 {
 179         int rc = 0;
 180
 181 #ifdef CONFIG_VSC7385_IMAGE
 182         if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
 183                 CONFIG_VSC7385_IMAGE_SIZE)) {
 184                 puts("Failure uploading VSC7385 microcode.\n");
 185                 rc = 1;
 186         }
 187 #endif
 188
 189         return rc;
 190 }
 191
 192 #if defined(CONFIG_OF_BOARD_SETUP)
 193
 194 void ft_board_setup(void *blob, bd_t *bd)
 195 {
 196 #ifdef CONFIG_PCI
 197         ft_pci_setup(blob, bd);
 198 #endif
 199         ft_cpu_setup(blob, bd);
 200         fdt_fixup_dr_usb(blob, bd);
 201 }
 202 #endif /* CONFIG_OF_BOARD_SETUP */